专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20150089162A1 DISTRIBUTED MEMORY OPERATIONS 审中-公开
标题翻译：分布式存储器操作
公开(公告)号：US20150089162A1
公开(公告)日：2015-03-26
申请号：US14037468
申请日：2013-09-26
申请人： Bushra Ahsan , Michael C. Adler , Neal C. Crago , Joel S. Emer , Aamer Jaleel , Angshuman Parashar , Michael I. Pellauer
发明人： Bushra Ahsan , Michael C. Adler , Neal C. Crago , Joel S. Emer , Aamer Jaleel , Angshuman Parashar , Michael I. Pellauer
IPC分类号： G06F3/06
CPC分类号： G06F13/1663 , G06F12/0646 , G06F13/1652 , G06F13/1684 , G06F2213/00
摘要： A technology for implementing a method for distributed memory operations. A method of the disclosure includes obtaining distributed channel information for an algorithm to be executed by a plurality of spatially distributed processing elements. For each distributed channel in the distributed channel information, the method further associates one or more of the plurality of spatially distributed processing elements with the distributed channel based on the algorithm.
摘要翻译：一种实现分布式存储器操作方法的技术。本公开的方法包括获得要由多个空间分布的处理元件执行的算法的分布式信道信息。对于分布式信道信息中的每个分布式信道，该方法还基于该算法进一步将多个空间分布处理单元中的一个或多个与分布式信道相关联。

2. 发明授权

US06704861B1 Mechanism for executing computer instructions in parallel 失效
标题翻译：并行执行计算机指令的机制
公开(公告)号：US06704861B1
公开(公告)日：2004-03-09
申请号：US08752729
申请日：1996-11-19
申请人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
发明人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
IPC分类号： G06F938
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/3865
摘要： A mechanism for executing computer instructions in parallel includes a compiler for generating and grouping instructions into a plurality of sets of instructions to be executed in parallel, each set having a unique identification. A computer system having a real state and a speculative state executes the sets in parallel, the computer system executing a particular set of instructions in the speculative state if the instructions of the particular set have dependencies which can not be resolved until the instructions are actually executed. The computer system generates speculative data while executing instructions in the speculative state. Logic circuits are provided to detect any exception conditions which occur while executing the particular set in the speculative state. If the particular set is subject to an exception condition, the instructions of the set are re-executed to resolve the exception condition, and to incorporate the speculative data in the real state of the computer system.
摘要翻译：用于并行执行计算机指令的机构包括：编译器，用于将指令生成和分组成并行执行的多组指令，每组具有唯一的标识。具有实际状态和推测状态的计算机系统并行地执行集合，如果特定集合的指令具有在实际执行指令之前无法解析的依赖关系，则计算机系统在推测状态下执行特定指令集。计算机系统在推测状态下执行指令时生成推测数据。提供逻辑电路以检测在推测状态下执行特定集合时发生的任何异常情况。如果特定集合受到异常条件的影响，则重新执行该集合的指令以解决异常条件，并将推测数据并入计算机系统的实际状态。

3. 发明授权

US5420990A Mechanism for enforcing the correct order of instruction execution 失效
标题翻译：执行指令执行顺序的机制
公开(公告)号：US5420990A
公开(公告)日：1995-05-30
申请号：US79494
申请日：1993-06-17
申请人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
发明人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3834 , G06F9/3842
摘要： An apparatus for enforcing that selected instructions are executed in a correct order, comprising a first content addressable memory for storing load addresses of data read from the memory by the selected instructions. The first content addressable memory comparing the store addresses with the load addresses of data to be written to the memory. The first content addressable memory generating a first signal, if one of the load addresses is identical to a subsequently compared one of the store addresses. The apparatus further including a second content addressable memory for storing and comparing states of the data read and written by the selected instructions. The second content addressable memory generating a second signal, if one of the stored states is identical to one of said compared states. The stored states including a program counter to repeat the execution of the selected instructions upon detecting the first and second signals.
摘要翻译：用于执行所选指令的装置以正确的顺序执行，包括用于存储由所选择的指令从存储器读取的数据的加载地址的第一内容可寻址存储器。第一内容可寻址存储器将存储地址与要写入存储器的数据的加载地址进行比较。所述第一内容可寻址存储器产生第一信号，如果所述加载地址之一与随后比较的一个所述存储地址相同。该装置还包括第二内容可寻址存储器，用于存储和比较由所选指令读和写的数据的状态。如果存储状态之一与所述比较状态之一相同，则第二内容可寻址存储器产生第二信号。所存储的状态包括在检测到第一和第二信号时重复所选指令的执行的程序计数器。

4. 发明授权

US5421022A Apparatus and method for speculatively executing instructions in a computer system 失效
标题翻译：用于在计算机系统中推测执行指令的装置和方法
公开(公告)号：US5421022A
公开(公告)日：1995-05-30
申请号：US79309
申请日：1993-06-17
申请人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
发明人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
IPC分类号： G06F9/38 , G06F9/30 , G06F9/312 , G06F9/42 , G06F9/44
CPC分类号： G06F9/3865 , G06F9/3842
摘要： A compiler groups instructions into sets. The sets of instructions are related by data and control dependencies which are unresolvable by the compiler. Sets of instructions having unresolved dependencies are executed in a speculative state of the computer system under the assumption that an exception condition will not occur. However, if an exception condition does occur while executing a set of instructions in the speculative state, that exception condition is detected and the set of instructions is re-executed in a real state of the computer system to resolve the exception condition.
摘要翻译：编译器将指令分组成集合。指令集是由编译器无法解决的数据和控制依赖关系相关的。在具有未解决的依赖性的指令集在假定不发生异常条件的假设下在计算机系统的推测状态下执行。然而，如果在推测状态下执行一组指令时发生异常情况，则检测该异常条件，并且在计算机系统的实际状态中重新执行指令集以解决异常状况。

5. 发明授权

US5428807A Method and apparatus for propagating exception conditions of a computer system 失效
标题翻译：传播计算机系统异常情况的方法和装置
公开(公告)号：US5428807A
公开(公告)日：1995-06-27
申请号：US79498
申请日：1993-06-17
申请人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowny
发明人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowny
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3865 , G06F9/3834 , G06F9/3842 , G06F9/3863
摘要： There is provided a mechanism for propagating exception conditions in a computer system when instructions are subject to exception conditions. The apparatus includes a set of data registers for storing data manipulated by the instructions of the computer system, and a set of state registers for storing speculative states of data manipulated by the instructions, there being one state register associated with each data register. Furthermore, the apparatus includes a logic circuit, coupled to the set of state registers, for propagating the states from a source one of the state registers to a destination one of the state registers, if data stored in an associated source one of the data registers are used as a source for an associated destination one of data registers, and if data stored in the source data register were manipulated by a particular instruction subject to an exception condition.
摘要翻译：当指令受到异常条件的限制时，提供了一种在计算机系统中传播异常情况的机制。该装置包括一组数据寄存器，用于存储由计算机系统的指令操纵的数据，以及一组状态寄存器，用于存储由指令操纵的数据的推测状态，存在与每个数据寄存器相关联的一个状态寄存器。此外，该装置包括耦合到一组状态寄存器的逻辑电路，用于将状态从状态寄存器中的一个状态寄存器传播到状态寄存器的目的地寄存器，如果数据存储在相关源中的一个数据寄存器被用作相关联的目的地数据寄存器的源，并且如果存储在源数据寄存器中的数据被受异常条件的特定指令操纵。

6. 发明授权

US5634023A Software mechanism for accurately handling exceptions generated by speculatively scheduled instructions 失效
标题翻译：用于准确处理由推测性安排的指令产生的异常的软件机制
公开(公告)号：US5634023A
公开(公告)日：1997-05-27
申请号：US270184
申请日：1994-07-01
申请人： Michael C. Adler , Steven O. Hobbs , Paul G. Lowney
发明人： Michael C. Adler , Steven O. Hobbs , Paul G. Lowney
IPC分类号： G06F9/38 , G06F9/30 , G06F15/16
CPC分类号： G06F9/3865 , G06F9/30072 , G06F9/3842
摘要： Methods for handling exceptions caused by speculatively scheduled instructions or predicated instructions executed within a computer program are described. The method for speculatively scheduled instructions includes checking at a commit point of a speculatively scheduled instruction, a semaphore associated with the speculatively scheduled instruction and branching to an error handling routine in the semaphore is set. A set semaphore indicates that an exception occurred when the speculatively scheduled instruction was executed. For a predicated instruction the method includes checking a predicate of a eliminated branch and a semaphore associated with the speculative instruction at a commit point of the speculative instruction and branching to an error handing routine if the semaphore indicates that an exception occurred when the speculative instruction was executed, and the predicate is true, which indicates that the speculative instruction was properly executed.
摘要翻译：描述用于处理在计算机程序中执行的由推测性调度的指令或预测指令引起的异常的方法。用于推测性调度指令的方法包括在推测性调度指令的提交点处检查与所述推测性调度指令相关联的信号量并分支到所述信号量中的错误处理例程。设置的信号量指示执行推测性调度指令时发生异常。对于预测指令，该方法包括在推测性指令的提交点处检查与被推断指令相关联的被消除的分支的谓词和分支到错误处理例程的信号量，如果信号量指示当推测性指令是执行，谓词为true，表示推测性指令已正确执行。

7. 发明授权

US5923863A Software mechanism for accurately handling exceptions generated by instructions scheduled speculatively due to branch elimination 失效
标题翻译：用于精确处理由于分支消除而推测的指令生成的异常的软件机制
公开(公告)号：US5923863A
公开(公告)日：1999-07-13
申请号：US548114
申请日：1995-10-25
申请人： Michael C. Adler , Steven O. Hobbs , Paul Geoffrey Lowney
发明人： Michael C. Adler , Steven O. Hobbs , Paul Geoffrey Lowney
IPC分类号： G06F9/38 , G06F9/45
CPC分类号： G06F9/3865 , G06F8/443 , G06F8/445 , G06F9/30072 , G06F9/3842
摘要： Methods for handling exceptions caused by speculatively scheduled instructions or predicated instructions executed within a computer program are described. The method for speculatively scheduled instructions includes checking at a commit point of a speculatively scheduled instruction, a semaphore associated with the speculatively scheduled instruction and branching to an error handling routine if the semaphore is set. A set semaphore indicates that an exception occurred when the speculatively scheduled instruction was executed. For a predicated instruction the method includes checking a predicate of an eliminated branch and a semaphore associated with the speculative instruction at a commit point of the speculative instruction and branching to an error handling routine if the semaphore indicates that an exception occurred when said speculative instruction was executed, and the predicate is true, which indicates that said speculative instruction was properly executed.
摘要翻译：描述用于处理在计算机程序中执行的由推测性调度的指令或预测指令引起的异常的方法。用于推测性调度指令的方法包括在推测性调度指令的提交点处检查与所述推测性调度指令相关联的信号量，并且如果设置了所述信号量则将其分支到错误处理例程。设置的信号量指示执行推测性调度指令时发生异常。对于预测指令，该方法包括在推测性指令的提交点处检查被排除的分支和与推测指令相关联的信号量的谓词，并分支到错误处理例程，如果信号量指示当所述推测指令为执行，谓词为true，表示所述推测指令已正确执行。

8. 发明授权

US5901308A Software mechanism for reducing exceptions generated by speculatively scheduled instructions 失效
标题翻译：用于减少由推测性安排的指令产生的异常的软件机制
公开(公告)号：US5901308A
公开(公告)日：1999-05-04
申请号：US617014
申请日：1996-03-18
申请人： Robert Cohn , Michael C. Adler , Paul Geoffrey Lowney
发明人： Robert Cohn , Michael C. Adler , Paul Geoffrey Lowney
IPC分类号： G06F9/38 , G06F9/45 , G06F11/34 , G06F9/00
CPC分类号： G06F8/445 , G06F11/3466 , G06F9/3842 , G06F9/3861
摘要： A method of compiling an application to reduce the occurrence of speculative exceptions is described. The method includes the steps of compiling the application to provide a speculation table and an executable file, and obtaining profile information about said compiled application using representative data sets. The compiler includes a scheduler unit for rearranging the order of the instructions in the application to provide optimal performance. The speculation table comprises a number of entries corresponding to the instructions of the application, each entry including a tag identifying the instruction and a semaphore indicating whether or not the instruction is likely to cause an exception. The executable file is run using a number of representative data sets to profile information identifying those instructions that result in exceptions, and the tag of the instruction is stored in a log file. After the profiling has completed, the tags of the instructions causing exceptions are used to set the semaphores in the speculation table corresponding to the tag. The application is then re-compiled. During the recompilation, those instructions with their semaphores set; i.e. those instructions causing exceptions, will not be speculatively scheduled by the compiler.
摘要翻译：描述了一种编译应用程序以减少投机异常发生的方法。该方法包括编译应用程序以提供猜测表和可执行文件的步骤，以及使用代表性数据集获取关于所述编译应用的简档信息。编译器包括用于重新排列应用程序中的指令的顺序以提供最佳性能的调度器单元。推测表包括与应用程序的指令对应的多个条目，每个条目包括标识指令的标签和指示该指令是否可能引起异常的信号量。可执行文件使用许多代表性数据集进行运行，以便对识别导致异常的那些指令进行简档信息，并将指令的标签存储在日志文件中。分析完成后，导致异常的指令的标签用于设置与标签对应的推测表中的信号量。然后应用程序被重新编译。在重新编译期间，设置了它们的信号量的指令; 即导致异常的那些指令不会被编译器推测地调度。

9. 发明授权

US06978462B1 Profiling execution of a sequence of events occuring during a profiled execution interval that matches time-independent selection criteria of events to be profiled 有权
标题翻译：对在匹配的事件的时间无关选择标准进行分析的执行间隔期间发生的事件序列的分析执行
公开(公告)号：US06978462B1
公开(公告)日：2005-12-20
申请号：US09332263
申请日：1999-06-11
申请人： Michael C. Adler , John S. Yates, Jr. , David L. Reese , Paul H. Hohensee , Stephen C. Purcell
发明人： Michael C. Adler , John S. Yates, Jr. , David L. Reese , Paul H. Hohensee , Stephen C. Purcell
IPC分类号： G06F3/00
CPC分类号： G06F11/348 , G06F9/30149 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/3851
摘要： A computer having an instruction pipeline and profile circuitry. The profile circuitry detects and records, without compiler assistance for execution profiling, profile information describing a sequence of events occurring in the instruction pipeline. The sequence includes every event occurring during a profiled execution interval that matches time-independent selection criteria of events to be profiled. The recording continues until a predetermined stop condition is reached. The profile circuitry detects the occurrence of a predetermined condition, after a non-profiled interval of execution, and then commences the profiled execution interval.
摘要翻译：具有指令流水线和简档电路的计算机。简档电路检测和记录，无需编译器协助执行分析，描述描述在指令流水线中发生的事件序列的简档信息。该序列包括在分析执行间隔期间发生的每个事件，其与要分析的事件的时间无关的选择标准相匹配。记录继续，直到达到预定的停止条件。配置文件电路在非分析执行间隔之后检测预定条件的发生，然后开始分析执行间隔。

10. 发明授权

US5627981A Software mechanism for accurately handling exceptions generated by instructions scheduled speculatively due to branch elimination 失效
标题翻译：用于精确处理由于分支消除而推测的指令生成的异常的软件机制
公开(公告)号：US5627981A
公开(公告)日：1997-05-06
申请号：US270192
申请日：1994-07-01
申请人： Michael C. Adler , Steven O. Hobbs , Paul G. Lowney
发明人： Michael C. Adler , Steven O. Hobbs , Paul G. Lowney
IPC分类号： G06F9/38 , G06F9/45
CPC分类号： G06F9/3865 , G06F8/443 , G06F8/445 , G06F9/30072 , G06F9/3842
摘要： Methods for handling exceptions caused by speculatively scheduled instructions or predicated instructions executed within a computer program are described. The method for speculatively scheduled instructions includes checking at a commit point of a speculatively scheduled instruction, a semaphore associated with the speculatively scheduled instruction and branching to an error handling routine if the semaphore is set. A set semaphore indicates that an exception occurred when the speculatively scheduled instruction was executed. For a predicated instruction the method includes checking a predicate of an eliminated branch and a semaphore associated with the speculative instruction at a commit point of the speculative instruction and branching to an error handling routine if the semaphore indicates that an exception occurred when said speculative instruction was executed, and the predicate is true, which indicates that said speculative instruction was properly executed.
摘要翻译：描述用于处理在计算机程序中执行的由推测性调度的指令或预测指令引起的异常的方法。用于推测性调度指令的方法包括在推测性调度指令的提交点处检查与所述推测性调度指令相关联的信号量，并且如果设置了所述信号量则将其分支到错误处理例程。设置的信号量指示执行推测性调度指令时发生异常。对于预测指令，该方法包括在推测性指令的提交点处检查被排除的分支和与推测指令相关联的信号量的谓词，并分支到错误处理例程，如果信号量指示当所述推测指令为执行，谓词为true，表示所述推测指令已正确执行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式