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1. 发明申请

US20050275005A1 Metal-insulator-metal (MIM) capacitor and method of fabricating the same 有权
标题翻译：金属绝缘体金属（MIM）电容器及其制造方法
公开(公告)号：US20050275005A1
公开(公告)日：2005-12-15
申请号：US11080567
申请日：2005-03-16
申请人： Seung-Man Choi , Ki-Chul Park , Bong-Seok Suh , Il-Ryong Kim
发明人： Seung-Man Choi , Ki-Chul Park , Bong-Seok Suh , Il-Ryong Kim
IPC分类号： H01L21/768 , H01L21/02 , H01L21/3205 , H01L21/822 , H01L21/8234 , H01L23/52 , H01L23/522 , H01L27/04 , H01L27/108 , H01L29/76
CPC分类号： H01L21/76841 , H01L21/76846 , H01L21/7685 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： In a MIM capacitor, and method of fabricating the same, the MIM capacitor includes an interlayer insulating layer on a semiconductor substrate, a lower metal interconnection and a lower metal electrode in the interlayer insulating layer, an intermetal dielectric layer covering the lower metal interconnection, the lower metal electrode, and the interlayer insulating layer, a via hole exposing the lower metal interconnection, an upper metal interconnection groove crossing over the via hole, at least one capacitor trench region exposing the lower metal electrode, an upper metal interconnection filling the upper metal interconnection groove, the upper metal interconnection being electrically connected to the lower metal interconnection through the via hole, a dielectric layer covering inner surfaces of the at least one capacitor trench region, and an upper metal electrode surrounded by the dielectric layer to fill the at least one capacitor trench region.
摘要翻译：在MIM电容器及其制造方法中，MIM电容器包括在半导体衬底上的层间绝缘层，层间绝缘层中的下部金属互连和下部金属电极，覆盖下部金属互连的金属间介电层，下金属电极和层间绝缘层，暴露下金属互连的通孔，与通孔相交的上金属互连槽，暴露下金属电极的至少一个电容器沟槽区，填充上金属互连的上金属互连金属互连槽，所述上金属互连通过所述通孔电连接到所述下金属互连，覆盖所述至少一个电容器沟槽区的内表面的电介质层和被所述电介质层包围的上金属电极以填充至少一个电容器沟槽区域。

2. 发明申请

US20050153544A1 Method of fabricating semiconductor device by forming diffusion barrier layer selectively and semiconductor device fabricated thereby 有权
标题翻译：通过选择性地形成扩散阻挡层制造半导体器件的方法和由此制造半导体器件
公开(公告)号：US20050153544A1
公开(公告)日：2005-07-14
申请号：US11033189
申请日：2005-01-11
申请人： Bong-Seok Suh , Ki-Chul Park , Seung-Man Choi , Il-Ryong Kim
发明人： Bong-Seok Suh , Ki-Chul Park , Seung-Man Choi , Il-Ryong Kim
IPC分类号： H01L21/3205 , H01L21/285 , H01L21/4763 , H01L21/768 , H01L23/52
CPC分类号： H01L21/76844 , H01L21/2855
摘要： In a method of fabricating a semiconductor device by selectively forming a diffusion barrier layer, and a semiconductor device fabricated thereby, a conductive pattern and an insulating layer, which covers the conductive pattern, are formed on a semiconductor substrate. The insulating layer is patterned, thereby forming an opening for exposing at least a portion of the conductive pattern. Then, a diffusion barrier layer is formed on the semiconductor substrate having the opening, using a selective deposition technique. The diffusion barrier layer is formed to a thickness that is less on the exposed conductive pattern than the thickness of the diffusion barrier layer on the insulating layer exposed inside the opening. Then, the diffusion barrier layer is etched, thereby forming a recessed diffusion barrier layer. In this manner, metal atoms are prevented from being diffused from a metal plug filling the opening or a metal interconnect to the insulating layer.
摘要翻译：在通过选择性地形成扩散阻挡层制造半导体器件的方法及其制造的半导体器件中，在半导体衬底上形成覆盖导电图案的导电图案和绝缘层。对绝缘层进行图案化，从而形成用于暴露导电图案的至少一部分的开口。然后，使用选择性沉积技术在具有开口的半导体衬底上形成扩散阻挡层。扩散阻挡层形成为暴露在导体图案上的厚度小于暴露在开口内部的绝缘层上的扩散阻挡层的厚度。然后，对扩散阻挡层进行蚀刻，从而形成凹陷扩散阻挡层。以这种方式，防止金属原子从填充开口的金属插塞或与绝缘层的金属互连扩散。

3. 发明授权

US07335590B2 Method of fabricating semiconductor device by forming diffusion barrier layer selectively and semiconductor device fabricated thereby 有权
标题翻译：通过选择性地形成扩散阻挡层制造半导体器件的方法和由此制造半导体器件
公开(公告)号：US07335590B2
公开(公告)日：2008-02-26
申请号：US11033189
申请日：2005-01-11
申请人： Bong-Seok Suh , Ki-Chul Park , Seung-Man Choi , Il-Ryong Kim
发明人： Bong-Seok Suh , Ki-Chul Park , Seung-Man Choi , Il-Ryong Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/2855
摘要： In a method of fabricating a semiconductor device by selectively forming a diffusion barrier layer, and a semiconductor device fabricated thereby, a conductive pattern and an insulating layer, which covers the conductive pattern, are formed on a semiconductor substrate. The insulating layer is patterned, thereby forming an opening for exposing at least a portion of the conductive pattern. Then, a diffusion barrier layer is formed on the semiconductor substrate having the opening, using a selective deposition technique. The diffusion barrier layer is formed to a thickness that is less on the exposed conductive pattern than the thickness of the diffusion barrier layer on the insulating layer exposed inside the opening. Then, the diffusion barrier layer is etched, thereby forming a recessed diffusion barrier layer. In this manner, metal atoms are prevented from being diffused from a metal plug filling the opening or a metal interconnect to the insulating layer.
摘要翻译：在通过选择性地形成扩散阻挡层制造半导体器件的方法及其制造的半导体器件中，在半导体衬底上形成覆盖导电图案的导电图案和绝缘层。对绝缘层进行图案化，从而形成用于暴露导电图案的至少一部分的开口。然后，使用选择性沉积技术在具有开口的半导体衬底上形成扩散阻挡层。扩散阻挡层形成为暴露在导电图案上的厚度小于暴露在开口内部的绝缘层上的扩散阻挡层的厚度。然后，对扩散阻挡层进行蚀刻，从而形成凹陷扩散阻挡层。以这种方式，防止金属原子从填充开口的金属插塞或与绝缘层的金属互连扩散。

4. 发明授权

US07332764B2 Metal-insulator-metal (MIM) capacitor and method of fabricating the same 有权
标题翻译：金属绝缘体金属（MIM）电容器及其制造方法
公开(公告)号：US07332764B2
公开(公告)日：2008-02-19
申请号：US11080567
申请日：2005-03-16
申请人： Seung-Man Choi , Ki-Chul Park , Bong-Seok Suh , Il-Ryong Kim
发明人： Seung-Man Choi , Ki-Chul Park , Bong-Seok Suh , Il-Ryong Kim
IPC分类号： H01L29/76
CPC分类号： H01L21/76841 , H01L21/76846 , H01L21/7685 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： In a MIM capacitor, and method of fabricating the same, the MIM capacitor includes an interlayer insulating layer on a semiconductor substrate, a lower metal interconnection and a lower metal electrode in the interlayer insulating layer, an intermetal dielectric layer covering the lower metal interconnection, the lower metal electrode, and the interlayer insulating layer, a via hole exposing the lower metal interconnection, an upper metal interconnection groove crossing over the via hole, at least one capacitor trench region exposing the lower metal electrode, an upper metal interconnection filling the upper metal interconnection groove, the upper metal interconnection being electrically connected to the lower metal interconnection through the via hole, a dielectric layer covering inner surfaces of the at least one capacitor trench region, and an upper metal electrode surrounded by the dielectric layer to fill the at least one capacitor trench region.
摘要翻译：在MIM电容器及其制造方法中，MIM电容器包括在半导体衬底上的层间绝缘层，层间绝缘层中的下部金属互连和下部金属电极，覆盖下部金属互连的金属间介电层，下金属电极和层间绝缘层，暴露下金属互连的通孔，与通孔相交的上金属互连槽，暴露下金属电极的至少一个电容器沟槽区，填充上金属互连的上金属互连金属互连槽，所述上金属互连通过所述通孔电连接到所述下金属互连，覆盖所述至少一个电容器沟槽区的内表面的电介质层和被所述电介质层包围的上金属电极以填充至少一个电容器沟槽区域。

5. 发明申请

US20070184649A1 Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics 有权
标题翻译：使用具有不同孔隙率特性的多个平坦化层在半导体衬底上形成双镶嵌互连结构的方法
公开(公告)号：US20070184649A1
公开(公告)日：2007-08-09
申请号：US11348428
申请日：2006-02-06
申请人： Kyoung-Woo Lee , Seung-Man Choi , Ja-Hum Ku , Ki-Chul Park , Sun Kim
发明人： Kyoung-Woo Lee , Seung-Man Choi , Ja-Hum Ku , Ki-Chul Park , Sun Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/31144
摘要： Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole. The first electrically insulating material, which has a relatively high degree of porosity, is then removed from the at least one via hole. This removal step may be performed using a relatively mild ashing process because of the high porosity of the first electrically insulating material.
摘要翻译：形成集成电路器件的方法包括图案化电绝缘层以支持其中的双镶嵌互连结构。图案化电绝缘层的步骤包括使用具有不同孔隙特性的多个平坦化层。在集成电路器件内形成互连结构可以包括在衬底上形成电绝缘层，并形成至少部分穿过电绝缘层延伸的至少一个通孔。至少一个通孔填充有具有第一孔隙率的第一电绝缘材料。填充的至少一个通孔然后被具有低于第一孔隙率的第二孔隙率的第二电绝缘材料层覆盖。选择性地回蚀第二电绝缘材料层以暴露至少一个通孔中的第一电绝缘材料的第一部分。电绝缘层被选择性蚀刻以在其中限定其中的沟槽，其暴露出至少一个通孔中的第一电绝缘材料的第二部分。然后从该至少一个通孔去除具有较高孔隙率的第一电绝缘材料。由于第一电绝缘材料的高孔隙率，该去除步骤可以使用相对温和的灰化过程进行。

6. 发明申请

US20100140747A1 Semiconductor devices 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100140747A1
公开(公告)日：2010-06-10
申请号：US12592924
申请日：2009-12-04
申请人： Seung-Man Choi , Soon-Sik Hwang , Ki-Chul Park , Gi-Bum Kim , Ki-Su Kim , Sang-Chul Lee , Bae-Kyoung Kim
发明人： Seung-Man Choi , Soon-Sik Hwang , Ki-Chul Park , Gi-Bum Kim , Ki-Su Kim , Sang-Chul Lee , Bae-Kyoung Kim
IPC分类号： H01L23/58 , H01L23/522 , H01L21/768
CPC分类号： H01L23/585 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01322 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042
摘要： In a method of manufacturing a semiconductor device, a pad including at least one insulating interlayer and at least one conductive wiring may be formed in a pad area of a substrate. At least one wiring may be formed adjacent to the conductive wiring. At least one insulation layer may be formed adjacent to the insulating interlayer. At least one crack preventing structure may be formed in the insulation layer. The crack preventing structure may continuously extend in the insulation layer and portions of the insulation layer may also be continuous. When a semiconductor device includes at least one crack preventing structure disposed adjacent to a pad, a degradation of the semiconductor chip caused by an external impact and/or a stress may be efficiently prevented by the crack preventing structure.
摘要翻译：在制造半导体器件的方法中，可以在衬底的焊盘区域中形成包括至少一个绝缘中间层和至少一个导电布线的焊盘。可以在导电布线附近形成至少一个布线。可以在绝缘中间层附近形成至少一个绝缘层。至少一个防裂结构可以形成在绝缘层中。防裂结构可以在绝缘层中连续延伸，并且绝缘层的部分也可以是连续的。当半导体器件包括邻近焊盘设置的至少一个防裂结构时，可以通过防裂结构有效地防止由外部冲击和/或应力引起的半导体芯片的劣化。

7. 发明授权

US07365025B2 Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics 有权
标题翻译：使用具有不同孔隙率特性的多个平坦化层在半导体衬底上形成双镶嵌互连结构的方法
公开(公告)号：US07365025B2
公开(公告)日：2008-04-29
申请号：US11348428
申请日：2006-02-06
申请人： Kyoung-Woo Lee , Seung-Man Choi , Ja-Hum Ku , Ki-Chul Park , Sun Oo Kim
发明人： Kyoung-Woo Lee , Seung-Man Choi , Ja-Hum Ku , Ki-Chul Park , Sun Oo Kim
IPC分类号： H01L21/311
CPC分类号： H01L21/76808 , H01L21/31144
摘要： Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole.
摘要翻译：形成集成电路器件的方法包括图案化电绝缘层以支持其中的双镶嵌互连结构。图案化电绝缘层的步骤包括使用具有不同孔隙特性的多个平坦化层。在集成电路器件内形成互连结构可以包括在衬底上形成电绝缘层，并形成至少部分穿过电绝缘层延伸的至少一个通孔。至少一个通孔填充有具有第一孔隙率的第一电绝缘材料。填充的至少一个通孔然后被具有低于第一孔隙率的第二孔隙率的第二电绝缘材料层覆盖。选择性地回蚀第二电绝缘材料层以暴露至少一个通孔中的第一电绝缘材料的第一部分。电绝缘层被选择性蚀刻以在其中限定其中的沟槽，其暴露出至少一个通孔中的第一电绝缘材料的第二部分。

8. 发明申请

US20070155165A1 Methods for forming damascene wiring structures having line and plug conductors formed from different materials 有权
标题翻译：用于形成具有由不同材料形成的线和插头导体的镶嵌线结构的方法
公开(公告)号：US20070155165A1
公开(公告)日：2007-07-05
申请号：US11323328
申请日：2005-12-30
申请人： Ki-Chul Park , Ja-Hum Ku , Seung-Man Choi
发明人： Ki-Chul Park , Ja-Hum Ku , Seung-Man Choi
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76877 , H01L23/485 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection structure includes depositing dielectric material on a semiconductor substrate and etching the dielectric material to form a dual damascene recess structure comprising a via hole and trench. A layer of first conductive material is then conformally deposited to fill the via hole with the first conductive material, and the layer of first conductive material is etched to remove the first conductive material from the trench and an upper region of the via hole below the trench. A layer of second conductive material is then deposited to fill the trench and upper region of the via hole with the second conductive material.
摘要翻译：提供了用于形成使用不同导体材料填充通孔和线沟槽的双镶嵌互连结构的方法。例如，用于形成互连结构的方法包括在半导体衬底上沉积介电材料并蚀刻电介质材料以形成包括通孔和沟槽的双镶嵌凹部结构。然后共形沉积第一导电材料层以用第一导电材料填充通孔，并且蚀刻第一导电材料层以从沟槽移除第一导电材料，并且在沟槽下方的通孔的上部区域。然后沉积第二导电材料层，以用第二导电材料填充通孔的沟槽和上部区域。

9. 发明授权

US06884710B2 Semiconductor device having multi-layer copper line and method of forming same 有权
标题翻译：具有多层铜线的半导体器件及其形成方法
公开(公告)号：US06884710B2
公开(公告)日：2005-04-26
申请号：US10338908
申请日：2003-01-09
申请人： Ki-Chul Park , Seung-Man Choi
发明人： Ki-Chul Park , Seung-Man Choi
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76847 , H01L21/76868 , H01L21/76873 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a lower copper line formed on a substrate, an interlayer insulating layer formed on the lower copper line, and an upper copper line formed on the interlayer insulating layer. A copper via contact extends through the interlayer insulating layer for electrically connecting the lower copper line and the upper copper line. A concave recess is formed within the lower copper line and is vertically aligned and arranged below the copper via contact. A patterned barrier layer is formed at a bottom portion of the concave recess, such that the lower copper line and the copper via contact are directly electrically connected at an interface along sides of the concave recess, without an intervening barrier layer.
摘要翻译：半导体器件包括形成在衬底上的下铜线，形成在下铜线上的层间绝缘层和形成在层间绝缘层上的上铜线。铜通孔接触件延伸穿过层间绝缘层，用于电连接下铜线和上铜线。在下铜线内部形成一个凹槽，并且垂直对齐并布置在铜通孔接触处的下方。图案化的阻挡层形成在凹形凹部的底部，使得下铜线和铜通路接触部在沿着凹形凹部的侧面的界面处直接电连接，而没有中间的阻挡层。

10. 发明授权

US07514354B2 Methods for forming damascene wiring structures having line and plug conductors formed from different materials 有权
标题翻译：用于形成具有由不同材料形成的线和插头导体的镶嵌线结构的方法
公开(公告)号：US07514354B2
公开(公告)日：2009-04-07
申请号：US11323328
申请日：2005-12-30
申请人： Ki-Chul Park , Ja-Hum Ku , Seung-Man Choi
发明人： Ki-Chul Park , Ja-Hum Ku , Seung-Man Choi
IPC分类号： H01L21/4763
CPC分类号： H01L21/76877 , H01L23/485 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection structure includes depositing dielectric material on a semiconductor substrate and etching the dielectric material to form a dual damascene recess structure including a via hole and trench. A layer of first conductive material is then conformally deposited to fill the via hole with the first conductive material, and the layer of first conductive material is etched to remove the first conductive material from the trench and an upper region of the via hole below the trench. A layer of second conductive material is then deposited to fill the trench and upper region of the via hole with the second conductive material.
摘要翻译：提供了用于形成使用不同导体材料填充通孔和线沟槽的双镶嵌互连结构的方法。例如，形成互连结构的方法包括在半导体衬底上沉积介电材料并蚀刻电介质材料以形成包括通孔和沟槽的双镶嵌凹部结构。然后共形沉积第一导电材料层以用第一导电材料填充通孔，并且蚀刻第一导电材料层以从沟槽移除第一导电材料，并且在沟槽下方的通孔的上部区域。然后沉积第二导电材料层，以用第二导电材料填充通孔的沟槽和上部区域。

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