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1. 发明申请

US20050138471A1 Apparatus, method, and system for logging diagnostic information 有权
标题翻译：用于记录诊断信息的装置，方法和系统
公开(公告)号：US20050138471A1
公开(公告)日：2005-06-23
申请号：US10715266
申请日：2003-11-17
申请人： Bitwoded Okbay , Carol Spanel , Andrew Walls
发明人： Bitwoded Okbay , Carol Spanel , Andrew Walls
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/364
摘要： A diagnostic tracing logger is presented for use in a multithread environment in which diagnostic trace log entries are captured and recorded. The trace logs are composed of sequences of memory addresses used to access instructions and operands, instruction op-codes and register specifiers, sequences of memory addresses, branch instructions or exceptions, the contents of registers or semiconductor memory locations, and the like. In one embodiment, a software module configures a plurality of buffers to capture bus traces, each trace triggered by a specific pattern. A buffer controller manages transfer of diagnostic trace information from the plurality of buffers to a diagnostic log without using processor memory cycles. The trace information is transferred to a selected buffer using a processor cache flush instruction. Diagnostic trace logging facilitates diagnosis of complex system and software interactions without the cost and overhead of prior art trace logging techniques.
摘要翻译：呈现诊断跟踪记录器，用于在其中捕获和记录诊断跟踪日志条目的多线程环境中使用。跟踪日志由用于访问指令和操作数，指令操作码和寄存器说明符，存储器地址序列，分支指令或异常，寄存器或半导体存储器位置的内容等的存储器地址的序列组成。在一个实施例中，软件模块配置多个缓冲器以捕获总线迹线，每个跟踪由特定模式触发。缓冲器控制器管理诊断跟踪信息从多个缓冲器到诊断日志的传送，而不使用处理器存储器周期。使用处理器高速缓存刷新指令将跟踪信息传输到选定的缓冲区。诊断跟踪记录便于诊断复杂的系统和软件交互，而不需要现有技术跟踪记录技术的成本和开销。

2. 发明申请

US20050160205A1 Method, apparatus and program storage device for managing dataflow through a processing system 失效
标题翻译：用于通过处理系统管理数据流的方法，装置和程序存储装置
公开(公告)号：US20050160205A1
公开(公告)日：2005-07-21
申请号：US10760019
申请日：2004-01-16
申请人： Lih-Chung Kuo , Andrew Moy , Carol Spanel , Andrew Walls
发明人： Lih-Chung Kuo , Andrew Moy , Carol Spanel , Andrew Walls
IPC分类号： G06F13/00 , G06F13/42
CPC分类号： G06F13/423
摘要： A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.
摘要翻译：公开了一种用于通过处理系统管理数据流的方法，装置和程序存储装置。缓冲器监视器维护和监视缓冲区的全部阈值，以控制数据总线的写入吞吐量。

3. 发明申请

US20050240833A1 Method for a voiding aliased tokens during abnormal communications 有权
标题翻译：在异常通信期间排除别名令牌的方法
公开(公告)号：US20050240833A1
公开(公告)日：2005-10-27
申请号：US10813519
申请日：2004-03-30
申请人： Michael Azevedo , Carol Spanel , Andrew Walls
发明人： Michael Azevedo , Carol Spanel , Andrew Walls
IPC分类号： G06F11/00
CPC分类号： H04L67/06
摘要： A data initiator device designates an initial data tag set for tagging data transfers to thereby attach data tags from the designated set to commands directed to data transfers between the data initiator device and a data target device subsequent to the designation of the initial data tag set. The data transfer commands are issued with the attached data tags from the designated data tag set until an occurrence of a reset error associated with one of the issued data transfer commands. In response to the reset error, the data initiator device designates a different data tag set for tagging data transfers to thereby attach data tags from the newly designated data tag set to commands directed to data transfers between the data initiator device and the data target device subsequent to the designation of the new data tag set.
摘要翻译：数据发起者设备指定用于标记数据传输的初始数据标签集，从而将数据标签从指定的集合附加到指定数据发起者设备与数据目标设备之间的数据传输的命令之后，指定初始数据标签集。数据传输命令与指定数据标签集中的附加数据标签一起发出，直到发生与所发出的数据传送命令之一相关联的复位错误。响应于复位错误，数据启动器设备指定用于标记数据传输的不同数据标签集，从而将新指定的数据标签集中的数据标签附加到指向数据发起器设备和数据目标设备之间的数据传输的命令之后指定新的数据标签集。

4. 发明申请

US20060010354A1 Self-healing cache system 有权
标题翻译：自愈缓存系统
公开(公告)号：US20060010354A1
公开(公告)日：2006-01-12
申请号：US10889380
申请日：2004-07-12
申请人： Michael Azevedo , Carol Spanel , Andrew Walls
发明人： Michael Azevedo , Carol Spanel , Andrew Walls
IPC分类号： G06F11/00
CPC分类号： G06F21/563 , G06F11/0715 , G06F11/0793 , G06F11/1064 , G06F12/126 , G06F21/564 , G06F2212/1032
摘要： A method, apparatus and program storage device for performing a self-healing cache process is described. At least one error affecting a cache is detected. The cache may have a matching address tag for a fetching operation. Based on the type of error, a self-healing cache process is performed based.
摘要翻译：描述了用于执行自愈高速缓存处理的方法，装置和程序存储装置。检测到至少一个影响缓存的错误。缓存可能具有用于提取操作的匹配地址标签。基于错误的类型，基于此进行自愈缓存处理。

5. 发明申请

US20050229019A1 Method, apparatus and program storage device for providing self-quiesced logic to handle an error recovery instruction 有权
标题翻译：用于提供自停逻辑以处理错误恢复指令的方法，装置和程序存储装置
公开(公告)号：US20050229019A1
公开(公告)日：2005-10-13
申请号：US10807075
申请日：2004-03-23
申请人： Michael Azevedo , Hugh McDevitt , Carol Spanel , Andrew Walls
发明人： Michael Azevedo , Hugh McDevitt , Carol Spanel , Andrew Walls
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0709 , G06F11/0757
摘要： A method, apparatus and program storage device for providing self-quiesced logic for handling an error recovery instruction such as a reset or self-test instruction. For example, during a reset or self test procedure, the logic is isolated without adversely affecting the local processor. Self-quiesced logic processes an error recovery instruction by monitoring the processor interface for an idle condition and withholding access to the local processor. Once the local processor interface has been quiesced and the internal logic paths are idle, the logic will proceed with the reset or self-test.
摘要翻译：一种用于提供用于处理诸如复位或自检指令的错误恢复指令的自静态逻辑的方法，装置和程序存储装置。例如，在复位或自检过程中，逻辑是隔离的，而不会对本地处理器造成不利影响。自静态逻辑通过监视处理器接口处于空闲状态并禁止对本地处理器的访问来处理错误恢复指令。一旦本地处理器接口停顿并且内部逻辑路径空闲，逻辑将继续进行复位或自检。

6. 发明申请

US20080028250A1 Method, apparatus and program storage device for providing clocks to multiple frequency domains using a single input clock of variable frequency 审中-公开
标题翻译：使用可变频率的单个输入时钟向多个频域提供时钟的方法，装置和程序存储装置
公开(公告)号：US20080028250A1
公开(公告)日：2008-01-31
申请号：US11879891
申请日：2006-08-29
申请人： Hugh McDevitt , Carol Spanel , Andrew Walls
发明人： Hugh McDevitt , Carol Spanel , Andrew Walls
IPC分类号： G06F1/04
CPC分类号： G06F1/06
摘要： A method, apparatus and program storage device for providing clocks to multiple frequency domains using a single input clock of variable frequency. Independent clock signals are generated at predetermined clock frequency targets in response to control signals that are based on a determined bus clock frequency.
摘要翻译：一种使用可变频率的单个输入时钟向多个频域提供时钟的方法，装置和程序存储装置。响应于基于确定的总线时钟频率的控制信号，在预定的时钟频率目标下产生独立的时钟信号。

7. 发明申请

US20060184736A1 Apparatus, system, and method for storing modified data 审中-公开
标题翻译：用于存储修改数据的装置，系统和方法
公开(公告)号：US20060184736A1
公开(公告)日：2006-08-17
申请号：US11061187
申请日：2005-02-17
申请人： Michael Benhase , Matthew Kalos , Carol Spanel , Andrew Walls
发明人： Michael Benhase , Matthew Kalos , Carol Spanel , Andrew Walls
IPC分类号： G06F12/14
CPC分类号： G06F11/1441 , G06F12/0804 , G06F12/0866 , G06F2212/2228 , G06F2212/282
摘要： An apparatus, system and method are disclosed for storing modified data. The apparatus includes a battery source for supplying backup power. The apparatus also includes a memory module for storing data. The memory module includes a backup portion and a non-backup portion. Only the backup portion is backed up by the battery source in the event of a power failure. A data flow module controls data flow into and out of the memory module. The data flow module stores modified data exclusively in the backup portion of the memory module.
摘要翻译：公开了用于存储修改数据的装置，系统和方法。该装置包括用于提供备用电力的电池源。该装置还包括用于存储数据的存储器模块。存储器模块包括备份部分和非备份部分。如果电源出现故障，只有备份部分由电池源备份。数据流模块控制进出存储器模块的数据流。数据流模块将修改的数据专门存储在存储器模块的备份部分中。

8. 发明申请

US20060107002A1 Method, system, and program for an adaptor to read and write to system memory 失效
公开(公告)号：US20060107002A1
公开(公告)日：2006-05-18
申请号：US10990039
申请日：2004-11-15
申请人： Michael Benhase , James Chen , Yu-Cheng Hsu , Matthew Kalos , Carol Spanel , Andrew Walls
发明人： Michael Benhase , James Chen , Yu-Cheng Hsu , Matthew Kalos , Carol Spanel , Andrew Walls
IPC分类号： G06F13/00
CPC分类号： G06F12/0866 , G06F12/1081
摘要： Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages in a memory device and I/O requests are generated to write the blocks in the buffer to the determined pages, wherein two I/O requests are generated to write to one block split between two pages in the memory device. The adaptor executes the generated I/O requests to write the blocks in the buffer to the determined pages in the memory device.

9. 发明申请

US20060203718A1 Method, apparatus and program storage device for providing a triad copy of storage data 有权
标题翻译：用于提供存储数据的三元组副本的方法，装置和程序存储装置
公开(公告)号：US20060203718A1
公开(公告)日：2006-09-14
申请号：US11079791
申请日：2005-03-14
申请人： Michael Benhase , Michael Hartung , Yu-Cheng Hsu , Carl Jones , William Verdoorn , Andrew Walls
发明人： Michael Benhase , Michael Hartung , Yu-Cheng Hsu , Carl Jones , William Verdoorn , Andrew Walls
IPC分类号： H04J3/14
CPC分类号： G06F11/2079 , G06F11/2058 , G06F11/2071
摘要： A method, apparatus and program storage device for maintaining data is provided that includes receiving primary data at a first node, receiving mirrored data from a second and third node at the first node, and mirroring data received at the first node to a second and third node.
摘要翻译：提供了一种用于维护数据的方法，装置和程序存储装置，其包括在第一节点处接收主数据，从第一节点处的第二和第三节点接收镜像数据，以及将在第一节点接收的数据镜像到第二和第三节点节点。

10. 发明申请

US20060200731A1 System and method of error detection for unordered data delivery 失效
公开(公告)号：US20060200731A1
公开(公告)日：2006-09-07
申请号：US11069777
申请日：2005-03-01
申请人： David Hepner , Andrew Walls
发明人： David Hepner , Andrew Walls
IPC分类号： H03M13/00
CPC分类号： H03M13/091
摘要： A system and method of error detection for unordered data delivery. A data set is received, the data set including a plurality of data segments, each having a descriptor; a data packet for each of the plurality of data segments, each of the data packets including the data segment and the descriptor for each of the plurality of data segments; and a source cyclic redundancy check (CRC) code for each of the data packets. The source CRC codes are stored as a source CRC table and a received CRC code is computed for a first data packet. It is determined whether the received CRC code for the first data packet is in the source CRC table and the first data packet is used when the received CRC code for the first data packet is in the source CRC table.

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