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1. 发明授权

US5142529A Method and means for transferring a data payload from a first SONET signal to a SONET signal of different frequency 失效
标题翻译：用于将数据有效载荷从第一SONET信号传送到不同频率的SONET信号的方法和装置
公开(公告)号：US5142529A
公开(公告)日：1992-08-25
申请号：US559636
申请日：1990-07-27
申请人： Bidyut Parruck , Daniel C. Upp
发明人： Bidyut Parruck , Daniel C. Upp
IPC分类号： G06F5/10 , G06F5/12 , H04J3/06 , H04J3/07 , H04J3/16 , H04L25/05
CPC分类号： G06F5/12 , H04J3/0623 , H04J3/076 , H04J3/1611 , H04L25/05 , G06F2205/123 , Y10S370/907
摘要： An apparatus and method for transferring a data payload (SPE) from a first substantially SONET signal into a second substantially SONET signal of different frequency is provided. The apparatus has: a circuit for extracting the SPE from the first SONET signal and sending the bytes of the SPE, according to a first clock, to a FIFO for storage; a circuit for obtaining the SPE bytes from the FIFO according to a second clock, for building the SPE into the second substantially SONET signal; and a circuit for comparing the relative byte phases of the first and second clocks. The byte phase comparison circuit serves two functions. In order to avoid read/write conflicts in the FIFO, it generates and sends a signal to the extracting circuit which causes the extracting circuit to change the byte phase (i.e. timing) at which bytes are sent to the FIFO. Also, in order to adjust the SPE for frequency differences between the first and second substantially SONET signals, the byte phase comparison circuits sends a signal to the circuit which builds the second substantially SONET signal when the two SONET signals have slipped a byte relative to each other. In response thereto, the second substantially SONET signal building circuit generates a negative or positive stuff.
摘要翻译：提供了一种用于将数据有效载荷（SPE）从第一基本SONET信号传送到不同频率的第二基本SONET信号的装置和方法。该装置具有：用于从第一SONET信号提取SPE并根据第一时钟将SPE的字节发送到FIFO以存储的电路; 用于根据第二时钟从FIFO获取SPE字节的电路，用于将SPE构建成第二基本SONET信号; 以及用于比较第一和第二时钟的相对字节相位的电路。字节相位比较电路有两个功能。为了避免FIFO中的读/写冲突，它产生并发送一个信号到提取电路，使得提取电路将字节发送到FIFO的字节相位（即定时）改变。此外，为了调整第一和第二基本SONET信号之间的频率差的SPE，当两个SONET信号相对于每个SONET信号滑过一个字节时，字节相位比较电路向建立第二基本SONET信号的电路发送信号其他。响应于此，第二基本上SONET信号建立电路产生负的或正的东西。

2. 发明授权

US5191582A Method and apparatus for the high speed modification of a packet address field of a transmitted packet in a frame relay system 失效
标题翻译：用于在帧中继系统中高速修改发送分组的分组地址字段的方法和装置
公开(公告)号：US5191582A
公开(公告)日：1993-03-02
申请号：US744894
申请日：1991-08-14
申请人： Daniel C. Upp
发明人： Daniel C. Upp
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04L12/56 , H04Q11/0478 , H04L2012/5645
摘要： Apparatus and methods for modifying the address field of a packet are disclosed. The apparatus preferably includes an HDLC controller which finds the start of the packet and generates a signal indicative of the same, a sequence controller which receives the signal from the HDLC controller and controls the apparatus in response thereto, an address decoder receives the address field bytes from the HDLC controller and decodes them to provide a DLCI code therefrom, a RAM which is programmed as a DLCI translation table with outgoing DLCI codes being located at addresses which equate to the incoming DLCI codes, an address encoder which receives the outgoing DLCI code from the RAM and generates therefrom outgoing address field bytes, and a FIFO for storing the outgoing address field bytes until output is possible. Bytes received by the HDLC controller during the modification of the packet header are stored by the HDLC controller until the outgoing address field bytes are received at the FIFO. The stored bytes are then also forwarded to the FIFO, and thereafter, incoming data can be forwarded directly to the FIFO. The provided apparatus for modifying the address field of a packet introduces a minimum of delay into the packet transfer and reduces the amount of data storage required to effect the address field modification.
摘要翻译：公开了用于修改分组的地址字段的装置和方法。该装置优选地包括一个HDLC控制器，它发现分组的开始并产生一个表示相同信号的信号，序列控制器从HDLC控制器接收信号并响应于此控制该设备，地址解码器接收地址字段从HDLC控制器解码并提供DLCI代码，RAM被编程为DLCI转换表，其中输出的DLCI代码位于等于输入的DLCI代码的地址处;地址编码器，其接收来自 RAM并产生其输出地址字段，以及用于存储输出地址字段字节的FIFO，直到输出成为可能。在HDLC控制器修改期间由HDLC控制器接收的字节由HDLC控制器存储，直到在FIFO处接收到输出地址字段为止。存储的字节然后也转发到FIFO，此后，输入数据可以直接转发到FIFO。所提供的用于修改分组的地址字段的设备对分组传输引入最小的延迟，并且减少了实现地址字段修改所需的数据存储量。

3. 发明授权

US5040170A System for cross-connecting high speed digital signals 失效
标题翻译：用于交叉连接高速数字信号的系统
公开(公告)号：US5040170A
公开(公告)日：1991-08-13
申请号：US283171
申请日：1988-12-09
申请人： Daniel C. Upp , William T. Cochran
发明人： Daniel C. Upp , William T. Cochran
IPC分类号： H04J3/00 , H04J3/16 , H04J3/22 , H04M7/00 , H04Q3/52 , H04Q11/04
CPC分类号： H04J3/1611 , G06F2205/123
摘要： A modular, expandable, non-blocking system for cross-connecting high speed digital signals is provided. The system is capable of connecting DSn, CEPTn, and STSn signals as desired, with lower rate signals being included as components of the high-rate signals or terminating on low speed lines, as desired. The system accomplishes its goals by converting all incoming signals into a substantially SONET format, and by processing all the signals in that format. The signals are typically cross-connected in the substantially SONET format, although an expandable non-blocking wide band cross-connect module is provided which cross-connects any like signals. If the outgoing signal is to be in other than SONET format, the substantially SONET formatted signal is reconverted into its outgoing format. To create a complete system, various modules are utilized, including: add/drop multiplexer means for add/drop applications of DS-0, DS-1, CEPTn signals, etc.; a SONET bus interface; a virtual tributary cross-connect module which cross-connects virtual tributary payloads in space, time, and phase to generate new substantially SONET formatted signals; a wide band cross-connect module; a DS-3/SONET converter; and front end interfaces including a DS3 line interface, and various STSn interfaces. The modules may be mixed and matched as desired to accommodate a multitude of applications.
摘要翻译：提供了用于交叉连接高速数字信号的模块化，可扩展的非阻塞系统。该系统能够根据需要连接DSn，CEPTn和STSn信号，根据需要，较低速率信号被包括作为高速率信号的分量或终止于低速线路。该系统通过将所有输入信号转换成基本SONET格式并通过处理该格式的所有信号来实现其目标。尽管提供了可扩展的非阻塞宽带交叉连接模块，这些信号通常以基本上SONET格式进行交叉连接，其交叉连接任何类似的信号。如果输出信号不是SONET格式，则基本上SONET格式的信号被转换为其输出格式。为了创建一个完整的系统，使用了各种模块，包括：用于DS-0，DS-1，CEPTn信号等的添加/删除应用的分插复用器装置; 一个SONET总线接口; 虚拟支路交叉连接模块，其跨越空间，时间和相位中的虚拟支路有效载荷，以产生新的基本上SONET格式的信号; 宽带交叉连接模块; DS-3 / SONET转换器; 和前端接口，包括DS3线路接口和各种STSn接口。可以根据需要混合和匹配模块以适应多种应用。

4. 发明授权

US4641301A Telecommunication switching system and priority arrangement used therein 失效
标题翻译：电信交换系统及其优先安排
公开(公告)号：US4641301A
公开(公告)日：1987-02-03
申请号：US701904
申请日：1985-02-15
申请人： Francoise C. G. Van Simaeys , Anna M. C. Leurs , Daniel C. Upp , Alan J. Lawrence , John M. Cotton
发明人： Francoise C. G. Van Simaeys , Anna M. C. Leurs , Daniel C. Upp , Alan J. Lawrence , John M. Cotton
IPC分类号： H04Q3/545 , H04Q11/04
CPC分类号： H04Q11/0407
摘要： A telecommunication switching system includes a number of control circuits each of which is common to a plurality of line circuits and is coupled through time division multiplex links with two processor controlled interface circuits which are further coupled to a switching network. Line scanning information is processed in the control circuits to reduce the work load of the processor controlled interface circuits. Said line scanning information is then transmitted in the TDM links to the processor controlled interface circuits. The transmission priority among the control circuits is determined by a priority arrangement established for the system. A channel assignment controls the allocation of channels of the TDM links leading to parts of the line circuits.
摘要翻译：电信交换系统包括多个控制电路，每个控制电路对于多个线路电路是共同的，并且通过时分复用链路与两个处理器控制的接口电路耦合，所述两个处理器控制的接口电路进一步耦合到交换网络。线路扫描信息在控制电路中进行处理，以减少处理器控制的接口电路的工作负载。所述行扫描信息然后在TDM链路中传送到处理器控制的接口电路。控制电路之间的传输优先级由为系统建立的优先级排列决定。信道分配控制通向部分线路电路的TDM链路的信道分配。

5. 发明申请

US20090141719A1 TRANSMITTING DATA THROUGH COMMUINCATION SWITCH 审中-公开
标题翻译：通过交换机传输数据
公开(公告)号：US20090141719A1
公开(公告)日：2009-06-04
申请号：US12272609
申请日：2008-11-17
申请人： Subhash C. Roy , David K. Toebes , Michael M. Renault , Steven E. Benoit , Igor Zhovnirovsky , Daniel C. Upp , William B. Lipp
发明人： Subhash C. Roy , David K. Toebes , Michael M. Renault , Steven E. Benoit , Igor Zhovnirovsky , Daniel C. Upp , William B. Lipp
IPC分类号： H04L12/56
CPC分类号： H04L12/6402 , H04J3/0682 , H04J3/0685 , H04J3/0688 , H04J2203/0025 , H04J2203/0026 , H04L7/10 , H04L2012/6413
摘要： Methods, systems, and apparatuses related to a communication switch are disclosed herein. In some embodiments, the communication switch may be configured to transmit TDM, ATM and/or packet data from an ingress service processor, through a plurality of switch elements, to an egress service processor. Other embodiments may be described and claimed.
摘要翻译：本文公开了与通信开关相关的方法，系统和装置。在一些实施例中，通信交换机可以被配置为将TDM，ATM和/或分组数据从入口服务处理器通过多个交换元件发送到出口服务处理器。可以描述和要求保护其他实施例。

6. 发明授权

US06646983B1 Network switch which supports TDM, ATM, and variable length packet traffic and includes automatic fault/congestion correction 有权
标题翻译：支持TDM，ATM和可变长度数据包流量的网络交换机，包括自动故障/拥塞纠正
公开(公告)号：US06646983B1
公开(公告)日：2003-11-11
申请号：US09717998
申请日：2000-11-21
申请人： Subhash C. Roy , Santanu Das , Daniel C. Upp , William B. Lipp , Jitender K. Vij , Michael M. Renault
发明人： Subhash C. Roy , Santanu Das , Daniel C. Upp , William B. Lipp , Jitender K. Vij , Michael M. Renault
IPC分类号： H04J314
CPC分类号： H04L12/6402 , H04L2012/6413
摘要： A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12×12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned. The last twenty slots of the frame are reserved for link overhead. Thus, the frame is capable of carrying the equivalent of 1,680 E-1 TDM signals. For ATM and packet data, a PDU (protocol data unit) of 16 slots is defined for a 64-byte payload. The PDUs are self-routed through the switch with a 28-bit routing tag which allows routing through seven switch stages using 4-bits per stage. Bandwidth is arbitrated among ATM and Packet connections while maintaining TDM timing.
摘要翻译：网络交换机包括至少一个端口处理器和至少一个开关元件。端口处理器具有SONET OC-x接口（用于TDM流量），UTOPIA接口（用于ATM和数据包流量）以及与交换机元件的接口。在一个实施例中，端口处理器具有等同于OC-48的总I / O带宽，并且交换单元具有12×12端口，总带宽为30Gbps。典型的交换机包括多个端口处理器和交换机元件。使用9行×1700个时隙的数据帧将ATM，TDM和分组数据从端口处理器通过一个或多个交换元件传输到相同或另一个端口处理器。每帧在125微秒内传输; 每行在13.89微秒。每个插槽包括一个4位标签加上一个4字节的有效载荷。时隙带宽为2.592Mbps，足够大以承载具有开销的E-1信号。 4位标签是交叉连接指针，当指定TDM连接时，该指针将被设置。帧的最后20个时隙被保留用于链路开销。因此，该帧能够承载1,680个E-1 TDM信号的等效物。对于ATM和分组数据，为64字节的有效载荷定义了16个时隙的PDU（协议数据单元）。 PDU通过具有28位路由标签的交换机进行自路由，该路由标签允许通过每个阶段使用4位的七个交换阶段进行路由。在保持TDM定时的同时，在ATM和分组连接之间仲裁带宽。

7. 发明授权

US06631130B1 Method and apparatus for switching ATM, TDM, and packet data through a single communications switch while maintaining TDM timing 有权
标题翻译：用于在保持TDM定时的同时通过单个通信交换机切换ATM，TDM和分组数据的方法和装置
公开(公告)号：US06631130B1
公开(公告)日：2003-10-07
申请号：US09717440
申请日：2000-11-21
申请人： Subhash C. Roy , Daniel C. Upp , William B. Lipp , Steven E. Benoit , Michael M. Renault
发明人： Subhash C. Roy , Daniel C. Upp , William B. Lipp , Steven E. Benoit , Michael M. Renault
IPC分类号： H04L1266
CPC分类号： H04L12/6402 , H04J3/0682 , H04J3/0688 , H04J2203/0025 , H04J2203/0026 , H04L7/10 , H04L2012/6413
摘要： A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12×12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned. The last twenty slots of the frame are reserved for link overhead. Thus, the frame is capable of carrying the equivalent of 1,680 E-1 TDM signals. For ATM and packet data, a PDU (protocol data unit) of 16 slots is defined for a 64-byte payload. The PDUs are self-routed through the switch with a 28-bit routing tag which allows routing through seven switch stages using 4-bits per stage. Bandwidth is arbitrated among ATM and Packet connections while maintaining TDM timing.
摘要翻译：网络交换机包括至少一个端口处理器和至少一个开关元件。端口处理器具有SONET OC-x接口（用于TDM流量），UTOPIA接口（用于ATM和数据包流量）以及与交换机元件的接口。在一个实施例中，端口处理器具有等同于OC-48的总I / O带宽，并且交换单元具有12×12端口，总带宽为30Gbps。典型的交换机包括多个端口处理器和交换机元件。使用9行×1700个时隙的数据帧将ATM，TDM和分组数据从端口处理器通过一个或多个交换元件传输到相同或另一个端口处理器。每帧在125微秒内传输; 每行在13.89微秒。每个插槽包括一个4位标签加上一个4字节的有效载荷。时隙带宽为2.592Mbps，足够大以承载具有开销的E-1信号。 4位标签是交叉连接指针，当指定TDM连接时，该指针将被设置。帧的最后20个时隙被保留用于链路开销。因此，该帧能够承载1,680个E-1 TDM信号的等效物。对于ATM和分组数据，为64字节的有效载荷定义了16个时隙的PDU（协议数据单元）。 PDU通过具有28位路由标签的交换机进行自路由，该路由标签允许通过每个阶段使用4位的七个交换阶段进行路由。在保持TDM定时的同时，在ATM和分组连接之间仲裁带宽。

8. 发明授权

US06243359B1 Methods and apparatus for managing traffic in an atm network 失效
标题翻译：用于管理大气网络中的流量的方法和装置
公开(公告)号：US06243359B1
公开(公告)日：2001-06-05
申请号：US09302200
申请日：1999-04-29
申请人： Subhash C. Roy , William B. Lipp , Daniel C. Upp , Alberto Bricca
发明人： Subhash C. Roy , William B. Lipp , Daniel C. Upp , Alberto Bricca
IPC分类号： H04J302
CPC分类号： H04Q11/0478 , H04L2012/5615 , H04L2012/5635 , H04L2012/5681
摘要： The apparatus includes a separate line side inlet queue for each GFR VC, a single network side outlet queue for all GFR VCs, a single network side inlet queue for all GFR VCs, a single line side outlet bulk processing queue with a post queue packet processor followed by separate line side outlet queues for each line, a network side outlet queue monitor, and a line side inlet queue controller. The network side outlet queue monitor is coupled to the line side inlet queue controller so that the network side outlet queue monitor can send messages to the line side inlet queue controller. According to one of the methods of the invention, the network side outlet queue monitor sends messages to the line side inlet queue controller directing the line side inlet queue controller to send data from the line side GFR queues based on the status of the network side outlet GFR queue. According to another method of the invention, the line to side inlet queue controller discards packets for a GFR VC if congestion is indicated. According to still another method of the invention, the post queue packet processor discards packets above the PCR if the size of the line side outlet bulk processing queue exceeds a threshold size and discards packets above the MCR if discarding packets above the PCR fails to sufficiently reduce the size of the line side outlet bulk processing queue.
摘要翻译：该设备包括用于每个GFR VC的单独的线路侧入口队列，用于所有GFR VC的单个网络侧出口队列，用于所有GFR VC的单个网络侧入口队列，具有后队列分组处理器的单个线路侧出口批量处理队列后面是每一行的单独的线路侧出口队列，网络侧出口队列监视器和线路侧入口队列控制器。网络侧出口队列监视器耦合到线路侧入口队列控制器，使网络侧出口队列监视器可以向线路侧入口队列控制器发送消息。根据本发明的一种方法，网络侧出口队列监视器向线路侧入口队列控制器发送消息，指示线路侧入口队列控制器基于网络侧出口的状态从线路侧GFR队列发送数据 GFR队列根据本发明的另一种方法，如果指示拥塞，则线对侧入口队列控制器丢弃用于GFR VC的分组。根据本发明的另一种方法，如果线路侧出口批量处理队列的大小超过阈值大小并且如果丢弃上述PCR上的分组，则丢弃MCR上方的分组，则后队列分组处理器丢弃PCR上方的分组，线路端口批量处理队列的大小。

9. 发明授权

US4201890A Multiport digital switching element 失效
标题翻译：多端口数字开关元件
公开(公告)号：US4201890A
公开(公告)日：1980-05-06
申请号：US888582
申请日：1978-03-17
申请人： Alan J. Lawrence , Jeffrey N. Denenberg , Murray Rubinstein , Daniel C. Upp
发明人： Alan J. Lawrence , Jeffrey N. Denenberg , Murray Rubinstein , Daniel C. Upp
IPC分类号： H04Q3/545 , G06F15/173 , H04Q11/04 , H04J3/06
CPC分类号： H04Q11/0407
摘要： A multiport single sided switching element is described for providing space and time switching between the input ports thereof and the output ports thereof in response to digital command signals for frames of digitally encoded data in a plurality of channels which is phase (bit) asynchronously coupled to any port of the switching element, the command signals being in for example the same channels as is the data. Every port of the single sided switching element is adaptable as either an inlet or an outlet and thus may be configured in a switching network as a one-sided, as a two-sided, or multisided switching element and includes a time division multiplexed bus for providing a space path between the ports of the switching element and further includes transmit and receive logic at each port responsive to command signals for coupling data from the input of any port to the TDM bus and additional logic at each port selectively responsive to command signals for bit synchronously extracting the data from the TDM bus in any channel thereby providing time slot interchange prior to coupling of data from the switching element to other switching elements. In a preferred embodiment, a sixteen port switching element is described.
摘要翻译：描述了多端口单侧开关元件，用于响应于多个通道中的数字编码数据的数字命令信号，在其输入端口和其输出端口之间提供空间和时间切换，该多个通道的相位（位）异步耦合到开关元件的任何端口，命令信号例如与数据相同的通道。单侧开关元件的每个端口可适用于入口或出口，并且因此可以在开关网络中被配置为单向的，作为双侧的或多路开关元件，并且包括时分复用的总线，用于在开关元件的端口之间提供空间路径，并且还包括响应于命令信号的每个端口处的发送和接收逻辑，用于将数据从任何端口的输入耦合到TDM总线，并且每个端口处的附加逻辑选择性地响应于命令信号在任何通道中同步地从TDM总线提取数据，从而在将数据从开关元件耦合到其它开关元件之前提供时隙交换。在一个优选实施例中，描述了十六端口开关元件。

10. 发明授权

US07409120B2 Integrated circuit for programmable optical delay 有权
标题翻译：用于可编程光延迟的集成电路
公开(公告)号：US07409120B2
公开(公告)日：2008-08-05
申请号：US11424012
申请日：2006-06-14
申请人： Geoff W. Taylor , Jianhong Cai , Daniel C. Upp
发明人： Geoff W. Taylor , Jianhong Cai , Daniel C. Upp
IPC分类号： G02B6/12
CPC分类号： H01Q1/525 , H03M3/43 , H03M3/454 , H03M3/456 , H04B1/525
摘要： Interference caused by the propagation of a transmit signal transmitted from a transmit antenna to a receive antenna is effectively cancelled by an improved signal cancellation system. The system includes an interference cancellation signal generator that generates a time-delayed and amplitude-reduced representation of said transmit signal. A summing stage is operably coupled to the interference cancellation signal generator and the receive antenna. The summing stage subtracts the time-delayed and amplitude-reduced representation of the transmit signal from a receive signal to substantially cancel the interference. The interference cancellation signal generator preferably includes a novel programmable optical delay line that introduces a variable amount of optical delay to an optical signal derived from said transmit signal in addition to a thyristor-based sigma delta modulator that converts samples of the transmit signal to into a digital signal in the optical domain.
摘要翻译：通过改进的信号消除系统有效地消除由从发射天线发射到接收天线的发射信号的传播引起的干扰。该系统包括产生所述发射信号的时间延迟和幅度减小的表示的干扰消除信号发生器。求和级可操作地耦合到干扰消除信号发生器和接收天线。求和级从接收信号中减去发射信号的时间延迟和幅度减小的表示，以基本上消除干扰。干扰消除信号发生器优选地包括一种新颖的可编程光学延迟线，其将可变量的光学延迟引入到从所述发射信号导出的光学信号，以及基于可控硅的Σ-Δ调制器，其将发射信号的采样转换为光域中的数字信号。

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