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1. 发明授权

US4377757A Logic module for integrated digital circuits 失效
标题翻译：集成数字电路逻辑模块
公开(公告)号：US4377757A
公开(公告)日：1983-03-22
申请号：US120070
申请日：1980-02-11
申请人： Bernd Konemann , Joachim Mucha , Gunther Zwiehoff
发明人： Bernd Konemann , Joachim Mucha , Gunther Zwiehoff
IPC分类号： G01R31/3181 , H03K3/335 , H03K21/00
CPC分类号： G01R31/31813
摘要： A logic module is disclosed for construction in an integrated digital circuit for promoting testing of the integrated circuit. A latch module is provided for functioning as a latch, as a back-coupled shift register, and in one embodiment of the invention as a linear shift register. The latch module is formed of a plurality of basic cells each of which has a flip-flop with associated logic gates, one of which is an exclusive OR gate. The latch module also has an input, parallel data inputs and parallel data data outputs. For functioning in the back-coupling mode, an exclusive OR gate is connected between at least one of the flip-flops and the input to the latch module.
摘要翻译：公开了用于在集成数字电路中构建用于促进集成电路的测试的逻辑模块。提供了一个闩锁模块，用作作为反向耦合移位寄存器的锁存器，并且在本发明的一个实施例中用作线性移位寄存器。锁存模块由多个基本单元形成，每个基本单元具有一个具有相关逻辑门的触发器，其中一个是异或门。锁存模块还具有输入，并行数据输入和并行数据数据输出。为了在反向耦合模式下工作，异或门连接在至少一个触发器和到锁存模块的输入端。

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