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1. 发明授权

US06625857B2 Method of forming a capacitive element 失效
标题翻译：形成电容元件的方法
公开(公告)号：US06625857B2
公开(公告)日：2003-09-30
申请号：US09773998
申请日：2001-02-01
申请人： Bernd K. Appelt , John M. Lauffer
发明人： Bernd K. Appelt , John M. Lauffer
IPC分类号： H01G700
CPC分类号： H05K1/162 , H05K1/0366 , H05K3/429 , H05K3/4641 , H05K2201/0195 , H05K2201/0209 , H05K2201/0355 , H05K2201/09309 , Y10T29/435 , Y10T29/49002 , Y10T29/4913 , Y10T29/49144 , Y10T29/5102
摘要： A method of forming a capacitive element for a circuit board or chip carrier having improved capacitance is provided. The element is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured followed by being fully cured. The lamination takes place by laminating a partially cured sheet to at least one other sheet of dielectric material and one of the conductive sheets. The total thickness of the two sheets of the dielectric component does not exceed about 4 rolls and preferably does not exceed about 3 mils; thus, the single dielectric sheet does not exceed about 2 mils and preferably does not exceed about 1.5 mils in thickness.
摘要翻译：提供一种形成用于具有改善的电容的电路板或芯片载体的电容元件的方法。元件由一对导电片形成，其间具有介质成分。电介质部件由两个或更多个电介质片材形成，其中至少一个电介质片材可部分固化，然后完全固化。通过将部分固化的片材层压到至少一种其它电介质材料片和导电片材之一中来进行层压。两片电介质组件的总厚度不超过约4卷，优选不超过约3密耳; 因此，单个电介质片材的厚度不超过约2密耳，优选不超过约1.5密耳。

2. 发明授权

US06574090B2 Printed circuit board capacitor structure and method 失效
标题翻译：印刷电路板电容器结构及方法
公开(公告)号：US06574090B2
公开(公告)日：2003-06-03
申请号：US09822591
申请日：2001-03-30
申请人： Bernd K. Appelt , John M. Lauffer
发明人： Bernd K. Appelt , John M. Lauffer
IPC分类号： H01G420
CPC分类号： H05K1/162 , H05K1/0366 , H05K3/429 , H05K3/4641 , H05K2201/0195 , H05K2201/0209 , H05K2201/0355 , H05K2201/09309 , Y10T428/12569 , Y10T428/12597 , Y10T428/12903 , Y10T428/24124 , Y10T428/2476 , Y10T428/24994 , Y10T428/249952 , Y10T428/252 , Y10T428/264 , Y10T428/265 , Y10T428/269
摘要： A capacitive element for a circuit board or chip carrier having improved capacitance and method of manufacturing the same is provided. The structure is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured or softened followed by being fully cured or hardened. The lamination takes place by laminating a partially cured or softened sheet to at least one other sheet of dielectric material and one of the sheets of conductive material. The total thickness of the two sheets of the dielectric component does not exceed about 4 mils and preferably does not exceed about 3 mils; thus, the single dielectric sheet does not exceed about 2 mils and preferably does not exceed about 1.5 mils in thickness. The use of two or more sheets of dielectric material makes it very unlikely that two or more defects in the sheets of dielectric material will align, thus greatly reducing the probability of a defect causing a failure in test or field use.
摘要翻译：提供了一种用于具有改进电容的电路板或芯片载体的电容元件及其制造方法。该结构由一对导电片形成，其间具有介质成分。电介质部件由两个或更多个电介质片形成，其中至少一个可部分固化或软化，然后完全固化或硬化。通过将部分固化或软化的片材层压到至少一种其它电介质材料片和导电材料片之一中来进行层压。两片电介质组件的总厚度不超过约4密耳，优选不超过约3密耳; 因此，单个电介质片材的厚度不超过约2密耳，优选不超过约1.5密耳。使用两层或更多层电介质材料使电介质材料片中的两个或多个缺陷非常不可能对齐，从而大大降低了导致测试或现场使用失败的缺陷的可能性。

3. 发明授权

US06781064B1 Printed circuit boards for electronic device packages having glass free non-conductive layers and method of forming same 失效
标题翻译：具有无玻璃非导电层的电子器件封装的印刷电路板及其形成方法
公开(公告)号：US06781064B1
公开(公告)日：2004-08-24
申请号：US09342584
申请日：1999-06-29
申请人： Bernd K. Appelt , Anilkumar C. Bhatt , James W. Fuller, Jr. , John M. Lauffer , Voya R. Markovich , William J. Rudik , William E. Wilson
发明人： Bernd K. Appelt , Anilkumar C. Bhatt , James W. Fuller, Jr. , John M. Lauffer , Voya R. Markovich , William J. Rudik , William E. Wilson
IPC分类号： H05K103
CPC分类号： H01L23/564 , H01L21/481 , H01L23/498 , H01L23/49894 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/181 , H05K1/036 , H05K1/0366 , H05K3/429 , H05K3/4626 , H05K3/4641 , H05K2201/0195 , H05K2201/0769 , H05K2201/09718 , H05K2201/09881 , H01L2924/00014 , H01L2924/00012
摘要： A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package. This printed circuit board includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.
摘要翻译：一种用于诸如球栅阵列封装或有机芯片载体封装的电子器件封装中的印刷电路板。该印刷电路板包括一个无玻璃的电介质，用于分离和绝缘电源芯，电路或电镀通孔，以防止导电材料沿玻璃基预浸料衬底迁移引起的短路。

4. 发明授权

US06391210B2 Process for manufacturing a multi-layer circuit board 失效
标题翻译：制造多层电路板的工艺
公开(公告)号：US06391210B2
公开(公告)日：2002-05-21
申请号：US09901848
申请日：2001-07-09
申请人： Bernd K. Appelt , John M. Lauffer , Voya R. Markovich , Irving Memis , David J. Russell
发明人： Bernd K. Appelt , John M. Lauffer , Voya R. Markovich , Irving Memis , David J. Russell
IPC分类号： H01B1300
CPC分类号： H05K3/4652 , H05K3/0023 , H05K3/0035 , H05K2203/0508 , H05K2203/0554
摘要： A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry. A further process is claimed for designing a multi-level circuit board product comprising making a prototype having the above structure in which the holes are manufactured by mechanical drilling or by laser or plasma ablation, evaluating the prototype, and then manufacturing a commercial circuit board having essentially the same structure and materials of construction as the prototype, but wherein the holes are manufactured by photoimaging techniques.
摘要翻译：一种电路板，其结构包括适用于通过激光烧蚀，等离子体消融或机械钻孔技术制造通孔的永久可光成像介电材料，以及通过光成像技术。还公开了一种用于在至少一侧具有第一级电路图案的衬底上制造多电平电路的工艺。该过程包括在第一级电路图案上施加永久可光成像电介质; 将永久可光成像电介质暴露于辐射; 将导电金属层层叠到电介质上; 通过机械钻孔或通过激光或等离子体消融在导电金属层和电介质中形成孔; 以及制作二级电路图案，并用导电材料填充所述孔，以电连接所述第一和第二层电路。要求设计多级电路板产品的另一方法包括制造具有上述结构的原型，其中通过机械钻孔或通过激光或等离子体烧蚀制造孔，评估原型，然后制造商业电路板，其具有基本上与原型相同的结构和结构材料，但是其中孔通过光成像技术制造。

5. 发明授权

US06427323B2 Method for producing conductor interconnect with dendrites 失效
标题翻译：用枝晶生产导体互连的方法
公开(公告)号：US06427323B2
公开(公告)日：2002-08-06
申请号：US09859690
申请日：2001-05-17
申请人： Bernd K. Appelt , Saswati Datta , Michael A. Gaynes , John M. Lauffer , James R. Wilcox
发明人： Bernd K. Appelt , Saswati Datta , Michael A. Gaynes , John M. Lauffer , James R. Wilcox
IPC分类号： H05K336
CPC分类号： H05K3/325 , H05K3/4614 , H05K2201/0373 , H05K2201/09536 , H05K2201/10666 , Y10T29/49126 , Y10T29/49128 , Y10T29/49165 , Y10T29/49194
摘要： A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.”
摘要翻译：提供了一种用于连接电子电路封装中的两个导电层的方法，包括以下步骤：在第一导电层的选定区域上形成枝晶，在第二导电层的选定区域上形成枝晶，在第一导电层上施加环氧粘合剂材料并且将第二导电层压缩附接到第一导电层，使得第一导电层上的枝晶与第二导电层上的枝晶接触。还要求保护的是包括用于根据本发明制造的电互连的树突的电子电路封装。本发明的替代实施例利用具有树突的中间表面金属代替“通孔”。

6. 发明授权

US5977642A Dendrite interconnect for planarization and method for producing same 失效
标题翻译：用于平坦化的树枝状互连及其制造方法
公开(公告)号：US5977642A
公开(公告)日：1999-11-02
申请号：US918085
申请日：1997-08-25
申请人： Bernd K. Appelt , Saswati Datta , Michael A. Gaynes , John M. Lauffer , James R. Wilcox
发明人： Bernd K. Appelt , Saswati Datta , Michael A. Gaynes , John M. Lauffer , James R. Wilcox
IPC分类号： H01L21/48 , H01L21/56 , H01L21/60 , H01L23/498 , H05K3/32 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/81 , H01L21/4853 , H01L21/563 , H01L23/49811 , H05K3/325 , H01L2224/13144 , H01L2224/16225 , H01L2224/73203 , H01L2224/81801 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/351 , H05K2201/10734 , H05K2201/10977 , H05K2203/0307 , H05K2203/0723 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155
摘要： A method is provided for connecting two conductive surfaces in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive surface, applying a dielectric insulation material over the first conductive surface such that the dendrites are exposed through the insulation material to leave a substantially planar surface of exposed dendrites, and placing a second conductive surface on top of the exposed dendrites. The second conductive surface may be a surface metal, a chip bump array, or a ball grid array. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection and planarization manufactured in accordance with the present invention.
摘要翻译：提供了一种用于连接电子电路封装中的两个导电表面的方法，包括以下步骤：在第一导电表面的选定区域上形成枝晶，在第一导电表面上施加介电绝缘材料，使得枝晶通过绝缘材料暴露于留下暴露的树突的基本上平坦的表面，并将第二导电表面放置在暴露的树突上。第二导电表面可以是表面金属，芯片凸块阵列或球栅阵列。还要求保护的是包含用于根据本发明制造的电互连和平坦化的树突的电子电路封装。

7. 发明授权

US06815085B2 Printed circuit board capacitor structure and method 失效
标题翻译：印刷电路板电容器结构及方法
公开(公告)号：US06815085B2
公开(公告)日：2004-11-09
申请号：US10436335
申请日：2003-05-12
申请人： Bernd K. Appelt , John M. Lauffer
发明人： Bernd K. Appelt , John M. Lauffer
IPC分类号： B32B1704
CPC分类号： H05K1/162 , H05K1/0366 , H05K3/429 , H05K3/4641 , H05K2201/0195 , H05K2201/0209 , H05K2201/0355 , H05K2201/09309 , Y10T428/12569 , Y10T428/12597 , Y10T428/12903 , Y10T428/24124 , Y10T428/2476 , Y10T428/24994 , Y10T428/249952 , Y10T428/252 , Y10T428/264 , Y10T428/265 , Y10T428/269
摘要： A capacitive element for a circuit board or chip carrier is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured followed by being fully cured. The partially cured sheet is laminated to at least one other sheet of dielectric material and one of the sheets of conductive material. The total thickness of the two sheets of the dielectric component does not exceed about 4 mils and preferably does not exceed about 3 mils. The use of two or more sheets of dielectric material makes it very unlikely that two or more defects in the sheets of dielectric material will align, thus greatly reducing the probability of a defect causing a failure in test or field use.

8. 发明授权

US06739046B1 Method for producing dendrite interconnect for planarization 失效
标题翻译：制造用于平坦化的枝晶互连的方法
公开(公告)号：US06739046B1
公开(公告)日：2004-05-25
申请号：US09576641
申请日：2000-05-22
申请人： Bernd K. Appelt , Saswati Datta , Michael A. Gaynes , John M. Lauffer , James R. Wilcox
发明人： Bernd K. Appelt , Saswati Datta , Michael A. Gaynes , John M. Lauffer , James R. Wilcox
IPC分类号： H05K302
CPC分类号： H01L24/81 , H01L21/4853 , H01L21/563 , H01L23/49811 , H01L2224/13144 , H01L2224/16225 , H01L2224/73203 , H01L2224/81801 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/351 , H05K3/325 , H05K2201/10734 , H05K2201/10977 , H05K2203/0307 , H05K2203/0723 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , H01L2924/00
摘要： A method is provided for connecting two conductive surfaces in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive surface, applying a dielectric insulation material over the first conductive surface such that the dendrites are exposed through the insulation material to leave a substantially planar surface of exposed dendrites, and placing a second conductive surface on top of the exposed dendrites. The second conductive surface may be a surface metal, a chip bump array, or a ball grid array. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection and planarization manufactured in accordance with the present invention.
摘要翻译：提供了一种用于连接电子电路封装中的两个导电表面的方法，包括以下步骤：在第一导电表面的选定区域上形成枝晶，在第一导电表面上施加介电绝缘材料，使得枝晶通过绝缘材料暴露于留下暴露的树突的基本上平坦的表面，并将第二导电表面放置在暴露的树突上。第二导电表面可以是表面金属，芯片凸块阵列或球栅阵列。还要求保护的是包含用于根据本发明制造的电互连和平坦化的树突的电子电路封装。

9. 发明授权

US06300575B1 Conductor interconnect with dendrites through film 失效
标题翻译：导体通过薄膜与树突互连
公开(公告)号：US06300575B1
公开(公告)日：2001-10-09
申请号：US08918084
申请日：1997-08-25
申请人： Bernd K. Appelt , Saswati Datta , Michael A. Gaynes , John M. Lauffer , James R. Wilcox
发明人： Bernd K. Appelt , Saswati Datta , Michael A. Gaynes , John M. Lauffer , James R. Wilcox
IPC分类号： H05K114
CPC分类号： H05K3/325 , H05K3/4614 , H05K2201/0373 , H05K2201/09536 , H05K2201/10666 , Y10T29/49126 , Y10T29/49128 , Y10T29/49165 , Y10T29/49194
摘要： A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.”
摘要翻译：提供了一种用于连接电子电路封装中的两个导电层的方法，包括以下步骤：在第一导电层的选定区域上形成枝晶，在第二导电层的选定区域上形成枝晶，在第一导电层上施加环氧粘合剂材料并且将第二导电层压缩附接到第一导电层，使得第一导电层上的枝晶与第二导电层上的枝晶接触。还要求保护的是包括用于根据本发明制造的电互连的树突的电子电路封装。本发明的替代实施例利用具有树突的中间表面金属代替“通孔”。

10. 发明授权

US06290860B1 Process for design and manufacture of fine line circuits on planarized thin film dielectrics and circuits manufactured thereby 有权
标题翻译：在平面化薄膜电介质和由此制造的电路上设计和制造细线电路的方法
公开(公告)号：US06290860B1
公开(公告)日：2001-09-18
申请号：US09283679
申请日：1999-04-01
申请人： Bernd K. Appelt , John M. Lauffer , Voya R. Markovich , Irving Memis , David J. Russell
发明人： Bernd K. Appelt , John M. Lauffer , Voya R. Markovich , Irving Memis , David J. Russell
IPC分类号： H01B1300
CPC分类号： H05K3/4652 , H05K3/0023 , H05K3/0035 , H05K2203/0508 , H05K2203/0554
摘要： A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry. A further process is claimed for designing a multi-level circuit board product comprising making a prototype having the above structure in which the holes are manufactured by mechanical drilling or by laser or plasma ablation, evaluating the prototype, and then manufacturing a commercial circuit board having essentially the same structure and materials of construction as the prototype, but wherein the holes are manufactured by photoimaging techniques.
摘要翻译：一种电路板，其结构包括适用于通过激光烧蚀，等离子体消融或机械钻孔技术制造通孔的永久可光成像介电材料，以及通过光成像技术。还公开了一种用于在至少一侧具有第一级电路图案的衬底上制造多电平电路的工艺。该过程包括在第一级电路图案上施加永久可光成像电介质; 将永久可光成像电介质暴露于辐射; 将导电金属层层叠到电介质上; 通过机械钻孔或通过激光或等离子体消融在导电金属层和电介质中形成孔; 以及制作二级电路图案，并用导电材料填充所述孔，以电连接所述第一和第二层电路。要求设计多级电路板产品的另一方法包括制造具有上述结构的原型，其中通过机械钻孔或通过激光或等离子体烧蚀制造孔，评估原型，然后制造商业电路板，其具有基本上与原型相同的结构和结构材料，但是其中孔通过光成像技术制造。

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