专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06571318B1 Stride based prefetcher with confidence counter and dynamic prefetch-ahead mechanism 有权
标题翻译：基于Stride的预取器，具有置信度计数器和动态预取提前机制
公开(公告)号：US06571318B1
公开(公告)日：2003-05-27
申请号：US09798469
申请日：2001-03-02
申请人： Benjamin T. Sander , William A. Hughes , Sridhar P. Subramanian , Teik-Chung Tan
发明人： Benjamin T. Sander , William A. Hughes , Sridhar P. Subramanian , Teik-Chung Tan
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A processor is described which includes a stride detect table. The stride detect table includes one or more entries, each entry used to track a potential stride pattern. Additionally, each entry includes a confidence counter. The confidence counter may be incremented each time another address in the pattern is detected, and thus may be indicative of the strength of the pattern (e.g., the likelihood of the pattern repeating). At a first threshold of the confidence counter, prefetching of the next address in the pattern (the most recent address plus the stride) may be initiated. At a second, greater threshold, a more aggressive prefetching may be initiated (e.g. the most recent address plus twice the stride). In some implementations, the prefetch mechanism including the stride detect table may replace a prefetch buffer and prefetch logic in the memory controller.
摘要翻译：描述了包括步幅检测表的处理器。步幅检测表包括一个或多个条目，每个条目用于跟踪潜在的步幅图案。另外，每个条目都包含一个置信计数器。每次检测到图案中的另一个地址时，置信度计数器可以递增，因此可以指示图案的强度（例如，图案重复的可能性）。在置信计数器的第一阈值处，可以启动模式中的下一个地址（最近的地址加大步）的预取。在第二个更大的阈值下，可以启动更积极的预取（例如，最近的地址加上步幅的两倍）。在一些实现中，包括步幅检测表的预取机制可以替代存储器控制器中的预取缓冲器和预取逻辑。

2. 发明申请

US20110197030A1 Latency Reduction for Cache Coherent Bus-Based Cache 有权
标题翻译：缓存相干总线缓存的延迟降低
公开(公告)号：US20110197030A1
公开(公告)日：2011-08-11
申请号：US13089050
申请日：2011-04-18
申请人： Brian P. Lilly , Sridhar P. Subramanian , Ramesh Gunna
发明人： Brian P. Lilly , Sridhar P. Subramanian , Ramesh Gunna
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/084
摘要： In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.
摘要翻译：在一个实施例中，系统包括耦合到互连的多个代理和耦合到互连的高速缓存。多个代理被配置为高速缓存数据。多个代理的第一代理被配置为通过发送存储器请求来在互连上发起事务，并且多个代理中的其他代理被配置为从互连窥探存储器请求。其他代理在交互的响应阶段提供响应。高速缓存被配置为检测存储器请求的命中，并且在响应阶段之前将事务的数据提供给第一代理，并且独立于响应。

3. 发明授权

US07949832B2 Latency reduction for cache coherent bus-based cache 有权
标题翻译：缓存相关总线缓存的延迟降低
公开(公告)号：US07949832B2
公开(公告)日：2011-05-24
申请号：US12714884
申请日：2010-03-01
申请人： Brian P. Lilly , Sridhar P. Subramanian , Ramesh Gunna
发明人： Brian P. Lilly , Sridhar P. Subramanian , Ramesh Gunna
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/084
摘要： In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.
摘要翻译：在一个实施例中，系统包括耦合到互连的多个代理和耦合到互连的高速缓存。多个代理被配置为高速缓存数据。多个代理的第一代理被配置为通过发送存储器请求来在互连上发起事务，并且多个代理中的其他代理被配置为从互连窥探存储器请求。其他代理在交互的响应阶段提供响应。高速缓存被配置为检测存储器请求的命中，并且在响应阶段之前将事务的数据提供给第一代理，并且独立于响应。

4. 发明申请

US20110040998A1 Oversampling-Based Scheme for Synchronous Interface Communication 失效
标题翻译：基于过采样的同步接口通信方案
公开(公告)号：US20110040998A1
公开(公告)日：2011-02-17
申请号：US12912521
申请日：2010-10-26
申请人： Sridhar P. Subramanian , Sukalpa Biswas , Vincent R. von Kaenel , Priya Ananthanarayanan
发明人： Sridhar P. Subramanian , Sukalpa Biswas , Vincent R. von Kaenel , Priya Ananthanarayanan
IPC分类号： G06F1/00 , G06F13/42 , G06F3/00
CPC分类号： G06F1/04
摘要： In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.
摘要翻译：在一个实施例中，在具有用于电路内部使用的内部时钟的电路的相关接口时钟的接口上同步通信的装置包括耦合以接收内部时钟和接口时钟的控制电路。控制电路被配置为在内部时钟的每个时钟周期多次对接口时钟进行采样，并且在内部时钟和接口时钟之间检测到采样的粒度的相位差。该装置包括被配置为在内部时钟域和接口时钟域之间传送数据的数据路径。数据路径被配置为在传送的数据上相对于内部时钟提供至少两个不同的定时。控制电路耦合到数据路径，并且被配置为响应于检测到的相位差来选择定时之一。

5. 发明授权

US07752366B2 Non-blocking address switch with shallow per agent queues 有权
标题翻译：非阻塞地址切换，每个代理队列较浅
公开(公告)号：US07752366B2
公开(公告)日：2010-07-06
申请号：US12263255
申请日：2008-10-31
申请人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
发明人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
IPC分类号： G06F13/00
CPC分类号： G06F13/362 , G06F13/4022
摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.
摘要翻译：在一个实施例中，开关被配置为耦合到互连。开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。多个存储位置被配置为存储由多个代理发送的多个请求。仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。在另一个实施例中，预期了一种方法。

6. 发明申请

US20100161905A1 Latency Reduction for Cache Coherent Bus-Based Cache 有权
标题翻译：缓存相干总线缓存的延迟降低
公开(公告)号：US20100161905A1
公开(公告)日：2010-06-24
申请号：US12714884
申请日：2010-03-01
申请人： Brian P. Lilly , Sridhar P. Subramanian , Ramesh Gunna
发明人： Brian P. Lilly , Sridhar P. Subramanian , Ramesh Gunna
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0831 , G06F12/084
摘要： In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.
摘要翻译：在一个实施例中，系统包括耦合到互连的多个代理和耦合到互连的高速缓存。多个代理被配置为高速缓存数据。多个代理的第一代理被配置为通过发送存储器请求来在互连上发起事务，并且多个代理中的其他代理被配置为从互连窥探存储器请求。其他代理在交互的响应阶段提供响应。高速缓存被配置为检测存储器请求的命中，并且在响应阶段之前将事务的数据提供给第一代理，并且独立于响应。

7. 发明授权

US08307236B2 Oversampling-based scheme for synchronous interface communication 失效
标题翻译：基于过采样的同步接口通信方案
公开(公告)号：US08307236B2
公开(公告)日：2012-11-06
申请号：US12912521
申请日：2010-10-26
申请人： Sridhar P. Subramanian , Sukalpa Biswas , Vincent R. von Kaenel , Priya Ananthanarayanan
发明人： Sridhar P. Subramanian , Sukalpa Biswas , Vincent R. von Kaenel , Priya Ananthanarayanan
IPC分类号： G06F1/00 , G06F1/12 , G06F3/00
CPC分类号： G06F1/04
摘要： In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.
摘要翻译：在一个实施例中，在具有用于电路内部使用的内部时钟的电路的相关接口时钟的接口上同步通信的装置包括耦合以接收内部时钟和接口时钟的控制电路。控制电路被配置为在内部时钟的每个时钟周期多次对接口时钟进行采样，并且在内部时钟和接口时钟之间检测到采样的粒度的相位差。该装置包括被配置为在内部时钟域和接口时钟域之间传送数据的数据路径。数据路径被配置为在传送的数据上相对于内部时钟提供至少两个不同的定时。控制电路耦合到数据路径，并且被配置为响应于检测到的相位差来选择定时之一。

8. 发明授权

US08219880B2 Combined single error correction/device kill detection code 有权
标题翻译：组合单错误纠正/设备杀死检测码
公开(公告)号：US08219880B2
公开(公告)日：2012-07-10
申请号：US13246736
申请日：2011-09-27
申请人： Brian P. Lilly , Robert Gries , Sridhar P. Subramanian , Sukalpa Biswas , Hao Chen
发明人： Brian P. Lilly , Robert Gries , Sridhar P. Subramanian , Sukalpa Biswas , Hao Chen
IPC分类号： H03M13/00
CPC分类号： H03M13/09 , G06F11/1004
摘要： In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.
摘要翻译：在一个实施例中，装置包括耦合到控制电路的检查/校正电路。检查/校正电路被耦合以接收数据块和相应的校验位。数据块作为N个传输被接收，每个传输包括M个数据位和L个校验位。检查/校正电路被配置为响应于M个数据位和L个校验位来检测M个数据位中K位的多个非重叠窗口中的每一个中的一个或多个错误。控制电路被配置为记录多个窗口中哪一个具有检测到的错误，并且如果多个窗口的给定窗口在块的N个传输中的每一个中都检测到错误，则控制电路被配置为发信号设备故障 K，L，M和N中的每一个是大于1的整数。

9. 发明授权

US08055975B2 Combined single error correction/device kill detection code 有权
标题翻译：组合单错误纠正/设备杀死检测码
公开(公告)号：US08055975B2
公开(公告)日：2011-11-08
申请号：US11758322
申请日：2007-06-05
申请人： Brian P. Lilly , Robert Gries , Sridhar P. Subramanian , Sukalpa Biswas , Hao Chen
发明人： Brian P. Lilly , Robert Gries , Sridhar P. Subramanian , Sukalpa Biswas , Hao Chen
IPC分类号： H03M13/00
CPC分类号： H03M13/09 , G06F11/1004
摘要： In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.
摘要翻译：在一个实施例中，装置包括耦合到控制电路的检查/校正电路。检查/校正电路被耦合以接收数据块和相应的校验位。数据块作为N个传输被接收，每个传输包括M个数据位和L个校验位。检查/校正电路被配置为响应于M个数据位和L个校验位来检测M个数据位中K位的多个非重叠窗口中的每一个中的一个或多个错误。控制电路被配置为记录多个窗口中哪一个具有检测到的错误，并且如果多个窗口的给定窗口在块的N个传输中的每一个中都检测到错误，则控制电路被配置为发信号设备故障 K，L，M和N中的每一个是大于1的整数。

10. 发明授权

US07970970B2 Non-blocking address switch with shallow per agent queues 有权
标题翻译：非阻塞地址开关，每个代理队列较浅
公开(公告)号：US07970970B2
公开(公告)日：2011-06-28
申请号：US12787865
申请日：2010-05-26
申请人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
发明人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
IPC分类号： G06F13/00
CPC分类号： G06F13/362 , G06F13/4022
摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.
摘要翻译：在一个实施例中，开关被配置为耦合到互连。开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。多个存储位置被配置为存储由多个代理发送的多个请求。仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。在另一个实施例中，预期了一种方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式