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1. 发明授权

US07337100B1 Physical resynthesis of a logic design 失效
标题翻译：逻辑设计的物理再合成
公开(公告)号：US07337100B1
公开(公告)日：2008-02-26
申请号：US10461921
申请日：2003-06-12
申请人： Michael D. Hutton , Joachim Pistorius , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Yean-Yow Hwang
发明人： Michael D. Hutton , Joachim Pistorius , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Yean-Yow Hwang
IPC分类号： G06F17/50 , G06F9/455 , G01R31/28
CPC分类号： G06F17/5068
摘要： A multiple-pass synthesis technique improves the performance of a design. In a specific embodiment, synthesis is performed in two or more passes. In a first pass, a first synthesis is performed, and in a second or subsequent pass, a second synthesis or resynthesis is performed. During the first synthesis, the logic will be mapped to for example, the logic structures (e.g., logic elements, LUTs, synthesis gates) of the target technology such as a programmable logic device. Alternatively a netlist may be provided from a third party. Before the second synthesis, a fast or abbreviated fit may be performed of the netlist to a specific device (e.g., specific programmable logic device product). Before the second synthesis, the netlist obtained from the first synthesis (or provided by a third party) is unmapped and then the second synthesis is performed. Since a partial fit is performed, the second synthesis has more visibility and optimize the logic better than by using a single synthesis pass. After the second synthesis pass, a more detailed fit is performed.
摘要翻译：多通道合成技术提高了设计的性能。在具体实施方案中，以两次或更多次通过进行合成。在第一次通过中，执行第一次合成，并且在第二次或随后的过程中进行第二次合成或再合成。在第一合成期间，逻辑将被映射到例如目标技术的逻辑结构（例如，逻辑元件，LUT，合成门），诸如可编程逻辑器件。或者，可以从第三方提供网表。在第二合成之前，可以将网表快速或缩写配合到特定设备（例如，特定的可编程逻辑设备产品）。在第二次合成之前，从第一次合成（或由第三方提供）获得的网表被未映射，然后进行第二次合成。由于执行部分拟合，所以第二合成比通过使用单个合成通路更好的可见性和优化逻辑。在第二次合成之后，进行更详细的拟合。

2. 发明授权

US07120883B1 Register retiming technique 有权
公开(公告)号：US07120883B1
公开(公告)日：2006-10-10
申请号：US10446650
申请日：2003-05-27
申请人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
发明人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5045
摘要： An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

3. 发明授权

US08402408B1 Register retiming technique 有权
公开(公告)号：US08402408B1
公开(公告)日：2013-03-19
申请号：US13338776
申请日：2011-12-28
申请人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
发明人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5045
摘要： An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

4. 发明授权

US08108812B1 Register retiming technique 有权
标题翻译：注册重新定时技术
公开(公告)号：US08108812B1
公开(公告)日：2012-01-31
申请号：US12749514
申请日：2010-03-30
申请人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
发明人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5045
摘要： An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.
摘要翻译：电子自动化系统对逻辑设计执行寄存器重新定时，这可能是可编程逻辑集成电路的逻辑设计。寄存器重新定时是设计中组合逻辑寄存器的移动或重排，以提高最大工作频率或fmax。在一个实现中，该系统包括机器可读代码，其可以存储在计算机上执行的诸如磁盘的计算机可读介质上。系统平衡时间，以便折中关键路径和非关键路径之间的延迟。注册重新定时可能会改变门级设计。

5. 发明授权

US07689955B1 Register retiming technique 失效
标题翻译：注册重新定时技术
公开(公告)号：US07689955B1
公开(公告)日：2010-03-30
申请号：US11513450
申请日：2006-08-30
申请人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
发明人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5045
摘要： An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.
摘要翻译：电子自动化系统对逻辑设计执行寄存器重新定时，这可能是可编程逻辑集成电路的逻辑设计。寄存器重新定时是设计中组合逻辑寄存器的移动或重排，以提高最大工作频率或fmax。在一个实现中，该系统包括机器可读代码，其可以存储在计算机上执行的诸如磁盘的计算机可读介质上。系统平衡时间，以便折中关键路径和非关键路径之间的延迟。注册重新定时可能会改变门级设计。

6. 发明授权

US07181703B1 Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage 有权
标题翻译：在计算机辅助设计中自动扫描参数以实现最佳性能和资源使用的技术
公开(公告)号：US07181703B1
公开(公告)日：2007-02-20
申请号：US10625505
申请日：2003-07-22
申请人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
发明人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
摘要翻译：提供了用于优化可编程集成电路上的电路设计的放置和合成的技术。在对已选择的输入参数编译不同的值后，对电路设计的性能进行分析。然后选择为输出量度产生最佳结果的输入参数值，以将电路设计合成并将其放置在可编程集成电路上。在一个实施例中，对于共享相同输入参数但是不同种子的所有测试编译器，对输出度量的值进行平均。在另一个实施例中，选择由用户确定的具有最佳输出度量的编译。这些技术允许用户自动交换编译时间以获得更优化的电路。

7. 发明授权

US07594208B1 Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage 有权
标题翻译：在计算机辅助设计中自动扫描参数以实现最佳性能和资源使用的技术
公开(公告)号：US07594208B1
公开(公告)日：2009-09-22
申请号：US11610392
申请日：2006-12-13
申请人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
发明人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
摘要翻译：提供了用于优化可编程集成电路上的电路设计的放置和合成的技术。在对已选择的输入参数编译不同的值后，对电路设计的性能进行分析。然后选择为输出量度产生最佳结果的输入参数值，以将电路设计合成并将其放置在可编程集成电路上。在一个实施例中，对于共享相同输入参数但是不同种子的所有测试编译器，对输出度量的值进行平均。在另一个实施例中，选择由用户确定的具有最佳输出度量的编译。这些技术允许用户自动交换编译时间以获得更优化的电路。

8. 发明授权

US07171633B1 Estimating quality during early synthesis 有权
标题翻译：早期综合评估质量
公开(公告)号：US07171633B1
公开(公告)日：2007-01-30
申请号：US10734905
申请日：2003-12-12
申请人： Yean-Yow Hwang , Babette van Antwerpen , Richard Yuan
发明人： Yean-Yow Hwang , Babette van Antwerpen , Richard Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer aided system includes a method of improving the accuracy, optimization, and minimization for the synthesis and mapping of logical functions into the logical structures of a target technology, such as the logic cells (e.g., look-up tables) of a programmable logic integrated circuit. In a specific implementation, the invention incorporates late-stage synthesis operations, such as found during a technology mapping operation, into earlier stage synthesis procedures. These late-stage synthesis operations are used to provide better estimates of delay and area of a final compiled design in order to guide optimization operations.
摘要翻译：计算机辅助系统包括提高逻辑功能的合成和映射到诸如可编程逻辑的逻辑单元（例如，查找表）的目标技术的逻辑结构中的精度，优化和最小化的方法集成电路。在具体实现中，本发明将晚期合成操作（诸如在技术映射操作期间发现）融入到早期阶段合成过程中。这些后期综合操作用于提供对最终编译设计的延迟和面积的更好估计，以指导优化操作。

9. 发明授权

US07671625B1 Omnibus logic element 有权
标题翻译：综合逻辑元素
公开(公告)号：US07671625B1
公开(公告)日：2010-03-02
申请号：US12043087
申请日：2008-03-05
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Michael Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Michael Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.
摘要翻译：公开了可以提供许多有利特征的LE。例如，LE可以提供LUT和输入共享的高效灵活的使用。 LE还可以灵活地使用一个或多个专用加法器并且包括寄存器功能。

10. 发明授权

US07911230B1 Omnibus logic element for packing or fracturing 有权
$Omnibus logic element for packing or fracturing$
标题翻译：用于包装或压裂的综合逻辑元件
公开(公告)号：US07911230B1
公开(公告)日：2011-03-22
申请号：US12425342
申请日：2009-04-16
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
摘要翻译：公开了可以提供多个有利特征的逻辑元件（LE）。例如，LE可以被配置为实现寄存器打包和/或可破碎的查找表。

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