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    • 1. 发明授权
    • System and method for model size reduction of an integrated circuit
utilizing net invariants
    • 使用网络不变量的集成电路的模型尺寸减小的系统和方法
    • US6049662A
    • 2000-04-11
    • US790261
    • 1997-01-27
    • Avijit SahaJames D. ChristianWilliam M. CanfieldGreg N. FifeNadeem Malik
    • Avijit SahaJames D. ChristianWilliam M. CanfieldGreg N. FifeNadeem Malik
    • G01R31/317G06F17/50
    • G06F17/5022G01R31/317
    • The present invention provides a system and method for verifying an integrated circuit model. The model includes a plurality of net variables. The system and method comprises generating a plurality of tests for simulating the integrated circuit, precalculating a reduced model based upon the generated tests, and evaluating the reduced model. In a preferred embodiment, the present invention includes restricting the test that are generated. Then net invariants for the integrated circuit are generated by translating the restricted plurality of tests to a smaller set of possible values for the net variables. Thereafter, a minimization algorithm or procedure is utilized to minimize the logic used in the particular system based upon the latch constraints. This system produces a reduced model which reduces the amount of the integrated circuit that must be simulated thereby increasing the simulation speed thereof. Accordingly, the present invention integrates an event-driven simulation and a cycle simulation in such a manner that the saving can be proportional to the size of the reduction of the model. In many environments this reduction is significant because it allows for a significant reduction in space which has a clear bearing on the verification process.
    • 本发明提供了一种用于验证集成电路模型的系统和方法。 该模型包括多个净变量。 该系统和方法包括生成多个用于模拟集成电路的测试,基于所生成的测试预先计算减少的模型,以及评估简化的模型。 在优选实施例中,本发明包括限制所产生的测试。 然后,通过将受限制的多个测试转换为较小的一组可变值来产生用于集成电路的净不变量。 此后,利用最小化算法或过程来最小化基于锁存约束的在特定系统中使用的逻辑。 该系统产生减少的模型,其减少必须模拟的集成电路的量,从而增加其模拟速度。 因此,本发明以如下方式集成了事件驱动的仿真和循环模拟,即节省可以与模型的减小的大小成比例。 在许多环境中,这种减少是重要的,因为它允许显着减少空间,这对验证过程有明确的影响。