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1. 发明授权

US07105901B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07105901B1
公开(公告)日：2006-09-12
申请号：US09114203
申请日：1998-07-13
申请人： Atsushi Miyanishi , Hisashi Matsumoto
发明人： Atsushi Miyanishi , Hisashi Matsumoto
IPC分类号： H01L29/78
CPC分类号： H01L27/0207 , H01L27/11807 , H01L29/41758
摘要： An active area (1) is provided with a concave part in its corner portion in a shape along a plan view. An insulating film (7) encloses this active area. A gate electrode (30) is arranged on a depressed region (DR) having an edge portion which is located on a low position due to the concave part, while a gate electrode (20) is arranged on an ordinary region (OR) having an edge portion projecting beyond the depressed region. A gate end cap (margin part) of the gate electrode (20) has a length x, while that of the gate electrode (30) has a length x+α. Thus provided is a semiconductor device causing no current defect between source/drain regions even if the active area and an insulating film defining this active area fail to satisfy the layout design following refinement of the semiconductor device.
摘要翻译：有源区域（1）在其角部分设置有沿着俯视图的形状的凹部。绝缘膜（7）包围该有效区域。栅电极（30）设置在凹陷区域（DR）上，凹陷区域（DR）具有由于凹部而位于低位置的边缘部分，而栅电极（20）布置在具有突出超过凹陷区域的边缘部分。栅电极（20）的栅极端帽（边缘部分）具有长度x，而栅电极（30）的栅极端帽具有长度x +α。因此，即使有源区域和限定该有源区域的绝缘膜不能满足半导体器件的细化之后的布局设计，也不会在源极/漏极区域之间引起电流缺陷的半导体器件。

2. 发明授权

US06269280B1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06269280B1
公开(公告)日：2001-07-31
申请号：US09113029
申请日：1998-07-13
申请人： Atsushi Miyanishi , Akira Yamazaki
发明人： Atsushi Miyanishi , Akira Yamazaki
IPC分类号： G06F1750
CPC分类号： H01L27/0207 , G06F17/5072 , G06F17/5077 , G11C2207/104 , H01L27/10894 , H01L27/10897
摘要： A DRAM control circuit or a test circuit describing a delay control cell is prepared. Automatic placement and routing is performed in relation to this circuit. Circuit simulation is executed at a step ST16. Delay control is performed with the delay control cell on the basis of a simulation result. Alternatively, delay control is performed with a circuit of the delay control cell on the basis of a test result. Thus, automatic placement and routing of at least either the DRAM control circuit or the test circuit provided in a DRAM is enabled.
摘要翻译：准备描述延迟控制单元的DRAM控制电路或测试电路。相对于该电路执行自动放置和布线。在步骤ST16执行电路仿真。基于模拟结果，利用延迟控制单元进行延迟控制。或者，基于测试结果，利用延迟控制单元的电路执行延迟控制。因此，DRAM中的DRAM控制电路或测试电路中的至少一个的自动放置和路由被启用。

3. 发明授权

US5699285A Normalization circuit device of floating point computation device 失效
标题翻译：浮点计算装置的归一化电路装置
公开(公告)号：US5699285A
公开(公告)日：1997-12-16
申请号：US651545
申请日：1996-05-22
申请人： Atsushi Miyanishi , Kazuyuki Iwaguro
发明人： Atsushi Miyanishi , Kazuyuki Iwaguro
IPC分类号： G06F7/00 , G06F5/01 , G06F7/76 , G06F7/38
CPC分类号： G06F5/012
摘要： It is an object to realize in a floating point computation device a normalization circuit device which carries out normalization, unnormalization and 0 function operation at high speed. A circuit (3) outputs 1 from the most significant bit for the number obtained by adding 1 to a decimal number value of the exponent part input signal (A). AND operation of the signal (A") and the mantissa part input signal (B) and OR operation of all bits of the value ((3) provide a control signal (G'). A circuit (2) represents in a binary value (B') a number obtained by subtracting 1 from a number value of the bit position of the leading 1 from the most significant bit of the signal (B). A circuit (6) subtracts the valve (B') from the signal (A) and a circuit (7b) selects the signal (H) and a 0 value according to the signal (G') to obtain an exponent part output signal (C) after normalization. A circuit (5) retrieves the respective bit states of the signal B from the most significant bit to render "1" only the bit state of the position of the leading 1. A circuit (7a) selects the signal (B") and a decoded signal (A') according to the signal (G') to obtain a moved amount (D). A shifter (8) shifts the signal (B) according to the signal (D) to obtain a mantissa part output signal (E) after normalization.
摘要翻译：在浮点计算装置中，实现高速进行归一化，非归一化和0功能操作的归一化电路装置。电路（3）从通过将1加到指数部分输入信号（A）的十进制数值获得的数字的最高有效位输出1。信号（A“）和尾数部分输入信号（B）的AND运算和值（（3））的所有位的”或“运算提供控制信号（G'），电路（2）以二进制值（B'）通过从信号（B）的最高有效位从前导1的位位置的数值减去1得到的数字，电路（6）从信号（B'）中减去阀（B'）（A）和电路（7b）根据信号（G'）选择信号（H）和0值，以在归一化后获得指数部分输出信号（C），电路（5）检索各个位状态信号B从最高有效位发送到“1”，仅使前导1的位置的位状态。电路（7a）根据（1）的选择信号（B“）和解码信号（A'），信号（G'）以获得移动量（D），移位器（8）根据信号（D）移位信号（B），以在归一化之后获得尾数部分输出信号（E）。

4. 发明授权

US08140220B2 In-vehicle apparatus 有权
标题翻译：车内装置
公开(公告)号：US08140220B2
公开(公告)日：2012-03-20
申请号：US12457033
申请日：2009-05-29
申请人： Seiji Fujikawa , Hidenori Kurose , Atsushi Miyanishi , Junji Amaya , Hidehiko Sowa , Kohichi Watanabe , Yasuo Nakashima
发明人： Seiji Fujikawa , Hidenori Kurose , Atsushi Miyanishi , Junji Amaya , Hidehiko Sowa , Kohichi Watanabe , Yasuo Nakashima
IPC分类号： G05D1/00
CPC分类号： G01C21/26
摘要： An object of the invention is to provide an in-vehicle apparatus and an in-vehicle system that can use a plurality of expansion modules. The in-vehicle apparatus includes a plurality of slots for connecting a plurality of modules, each having a connector for connection, to expand capabilities of the in-vehicle apparatus, and a control unit for identifying the kind of each of the plurality of modules connected to the plurality of slots.
摘要翻译：本发明的目的是提供一种可以使用多个扩展模块的车载设备和车载系统。车载装置包括用于连接多个模块的多个槽，每个模块具有用于连接的连接器，以扩展车载设备的能力;以及控制单元，用于识别连接的多个模块中的每一个的种类到多个时隙。

5. 发明授权

US07898896B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07898896B2
公开(公告)日：2011-03-01
申请号：US12410868
申请日：2009-03-25
申请人： Atsushi Miyanishi
发明人： Atsushi Miyanishi
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C7/1006 , G11C11/412 , G11C2207/108
摘要： The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays.
摘要翻译：本发明提供一种能够简化具有半导体存储部的半导体器件的布局结构的技术，其中输入端口和输出端口彼此分离，并且包括旁路功能。在用作半导体器件的半导体存储器部分的半导体存储器件中，在旁路模式中，输出缓冲器将从输入缓冲器电路延伸到输出缓冲器电路的旁路线传输的输入数据输出到输出港口。在半导体存储器件的布局结构中，在平面图中，在输入缓冲器电路和输出缓冲器电路之间布置存储单元阵列，并且在存储单元阵列之间布置旁路线。

6. 发明申请

US20070047283A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070047283A1
公开(公告)日：2007-03-01
申请号：US11508288
申请日：2006-08-23
申请人： Atsushi Miyanishi
发明人： Atsushi Miyanishi
IPC分类号： G11C5/02
CPC分类号： G11C8/16 , G11C7/1006 , G11C11/412 , G11C2207/108
摘要： The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays.
摘要翻译：本发明提供一种能够简化具有半导体存储部的半导体器件的布局结构的技术，其中输入端口和输出端口彼此分离，并且包括旁路功能。在用作半导体器件的半导体存储器部分的半导体存储器件中，在旁路模式中，输出缓冲器将从输入缓冲器电路延伸到输出缓冲器电路的旁路线传输的输入数据输出到输出港口。在半导体存储器件的布局结构中，在平面图中，在输入缓冲器电路和输出缓冲器电路之间布置存储单元阵列，并且在存储单元阵列之间布置旁路线。

7. 发明授权

US06310815B1 Multi-bank semiconductor memory device suitable for integration with logic 失效
标题翻译：适合与逻辑集成的多存储半导体存储器件
公开(公告)号：US06310815B1
公开(公告)日：2001-10-30
申请号：US09131346
申请日：1998-08-07
申请人： Tadato Yamagata , Akira Yamazaki , Shigeki Tomishima , Yoshio Yukinari , Makoto Hatakenaka , Atsushi Miyanishi
发明人： Tadato Yamagata , Akira Yamazaki , Shigeki Tomishima , Yoshio Yukinari , Makoto Hatakenaka , Atsushi Miyanishi
IPC分类号： G11C800
CPC分类号： G11C5/14 , G11C8/12
摘要： Subbanks are arranged in four regions of a DRAM macro having a rectangular shape, bank control circuits are arranged in a prescribed region between these subbanks, and internal read/write data buses are arranged in a region different from the region where the bank control circuits are arranged. Since there is no crossing of the bank control circuits and the internal read/write data buses, the bank control circuits can be efficiently arranged to reduce the layout area. Accordingly, a semiconductor integrated circuit device including multi-bank memories which operates stably at high speed can be provided without increase of an area occupied by a chip.
摘要翻译：子行排列在具有矩形形状的DRAM宏的四个区域中，组控制电路布置在这些子行之间的规定区域中，并且内部读/写数据总线布置在与存储体控制电路的区域不同的区域中安排。由于银行控制电路和内部读/写数据总线没有交叉，因此可以有效地布置存储体控制电路以减少布局面积。因此，可以在不增加芯片占有面积的情况下提供包括以高速稳定运行的多存储体存储器的半导体集成电路器件。

8. 发明申请

US20090185431A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090185431A1
公开(公告)日：2009-07-23
申请号：US12410868
申请日：2009-03-25
申请人： Atsushi Miyanishi
发明人： Atsushi Miyanishi
IPC分类号： G11C7/00 , G11C8/08 , G11C8/16
CPC分类号： G11C8/16 , G11C7/1006 , G11C11/412 , G11C2207/108
摘要： The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays.
摘要翻译：本发明提供一种能够简化具有半导体存储部的半导体器件的布局结构的技术，其中输入端口和输出端口彼此分离，并且包括旁路功能。在用作半导体器件的半导体存储器部分的半导体存储器件中，在旁路模式中，输出缓冲器将从输入缓冲器电路延伸到输出缓冲器电路的旁路线传输的输入数据输出到输出港口。在半导体存储器件的布局结构中，在平面图中，在输入缓冲器电路和输出缓冲器电路之间布置存储单元阵列，并且在存储单元阵列之间布置旁路线。

9. 发明申请

US20070168773A1 Semiconductor memory unit with repair circuit 审中-公开
标题翻译：半导体存储单元具有修复电路
公开(公告)号：US20070168773A1
公开(公告)日：2007-07-19
申请号：US11712443
申请日：2007-03-01
申请人： Atsushi Miyanishi
发明人： Atsushi Miyanishi
IPC分类号： G11C29/00
CPC分类号： G11C29/806
摘要： A semiconductor memory unit with a repair circuit includes a controller, a 2-to-1 selector, an address decoder and an address comparator. The controller supplies the 2-to-1 selector and the address comparator with a setup signal to carry out the following control. When the 2-to-1 selector is controlled to supply the address decoder with a repair address signal, the address comparator is controlled to have a repair signal information holding section, which is installed in the address comparator, hold the repair address decoded by the address decoder. When the 2-to-1 selector is controlled to supply the address decoder with a read/write address signal, the address comparator is controlled to compare the read/write address with the repair address. The semiconductor memory unit can obviate the need for a repair address decoder, thereby reducing the unit area.
摘要翻译：具有修复电路的半导体存储器单元包括控制器，2对1选择器，地址解码器和地址比较器。控制器为2对1选择器和地址比较器提供设置信号，以执行以下控制。当控制2对1选择器为地址解码器提供修复地址信号时，地址比较器被控制为具有修复信号信息保持部分，其被安装在地址比较器中，保持由地址解码器。当控制2对1选择器为地址解码器提供读/写地址信号时，地址比较器被控制以将读/写地址与修复地址进行比较。半导体存储器单元可以避免对修复地址解码器的需要，从而减少单位面积。

10. 发明授权

US06535453B2 Semiconductor memory device 有权
公开(公告)号：US06535453B2
公开(公告)日：2003-03-18
申请号：US10056111
申请日：2002-01-28
申请人： Koji Nii , Atsushi Miyanishi
发明人： Koji Nii , Atsushi Miyanishi
IPC分类号： G11C800
CPC分类号： G11C8/16 , G11C7/18 , H01L27/1104
摘要： In the construction of a P-well area including a pair of CMOS inverters and a N-well area of a multi-port SRAM cell, the P-well area is divided into two P-well areas. These two P-well areas are disposed on two sides of the N-well area. A layout is provided such that the boundaries between the P-well areas and the N-well area are parallel to bit lines. Two access gates are located in one P-well area and two access gates are located in the other P-well area. Thus, the bit lines can be made shorter, and the amount of wiring can be reduced.

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