专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20170017593A1 PROACTIVE QUALITY OF SERVICE IN MULTI-MATRIX SYSTEM BUS 审中-公开
标题翻译：多矩阵系统总线的服务质量
公开(公告)号：US20170017593A1
公开(公告)日：2017-01-19
申请号：US15187619
申请日：2016-06-20
申请人： Atmel Corporation
发明人： Franck Lunadier , Eric Matulik , Renaud Tiennot
IPC分类号： G06F13/362 , G06F13/40
CPC分类号： G06F13/362 , G06F13/368 , G06F13/4022 , G06F13/4068
摘要： A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a network transfer request path, a highest priority value coming from an upstream arbitration node or master that has a current bus request pending at the arbitration node. The bus system ensures that any last downstream arbitration node knows at any time which is the highest priority request pending in the network transfer request path from the masters that are competing to share the bus layer switches and arbitration nodes in the network transfer request path.
摘要翻译：公开了一种多矩阵总线系统，其通过在网络传送请求路径中通过仲裁节点尽可能快地传播来自上游仲裁节点或主机的最高优先级值来提供主动服务质量（QoS）当前总线请求在仲裁节点挂起。总线系统确保任何最后一个下行仲裁节点在任何时候都知道网络传输请求路径中等待的最高优先级请求是来自正在竞争共享总线层交换机和仲裁节点的网络传输请求路径中的主机。

2. 发明申请

US20150186314A1 MICROCONTROLLER RESOURCE SHARING 有权
标题翻译：微控制器资源共享
公开(公告)号：US20150186314A1
公开(公告)日：2015-07-02
申请号：US14659074
申请日：2015-03-16
申请人： Atmel Corporation
发明人： Guillaume Pean , Franck Lunadier , Alain Vergnes
IPC分类号： G06F13/364 , G06F13/28 , H04L9/06 , G06F13/40
CPC分类号： G06F13/364 , G06F13/00 , G06F13/28 , G06F13/4022 , H04L9/0631
摘要： A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.
摘要翻译：系统包括一个或多个主模块，其被配置为执行嵌入在非暂时机器可读介质中并由处理器控制的指令。该系统还包括一个或多个外围模块，其被配置为执行嵌入在非暂时机器可读介质中并且可由处理器控制的指令。该系统还包括具有嵌入在非暂时机器可读介质中的指令的系统总线，并且被配置为允许处理器与一个或多个外围模块之间的数据传输。一个或多个外围模块的数据处理模块包括主接口和从接口。主接口和从接口都耦合到系统总线。

3. 发明授权

US09317462B2 Microcontroller peripheral data transfer redirection for resource sharing 有权
标题翻译：微控制器外围数据传输重定向用于资源共享
公开(公告)号：US09317462B2
公开(公告)日：2016-04-19
申请号：US14659074
申请日：2015-03-16
申请人： Atmel Corporation
发明人： Guillaume Pean , Franck Lunadier , Alain Vergnes
IPC分类号： G06F13/00 , G06F13/364 , G06F13/28 , G06F13/40 , H04L9/06
CPC分类号： G06F13/364 , G06F13/00 , G06F13/28 , G06F13/4022 , H04L9/0631
摘要： A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.
摘要翻译：系统包括一个或多个主模块，其被配置为执行嵌入在非暂时机器可读介质中并由处理器控制的指令。该系统还包括一个或多个外围模块，其被配置为执行嵌入在非暂时机器可读介质中并且可由处理器控制的指令。该系统还包括具有嵌入在非暂时机器可读介质中的指令的系统总线，并且被配置为允许处理器与一个或多个外围模块之间的数据传输。一个或多个外围模块的数据处理模块包括主接口和从接口。主接口和从接口都耦合到系统总线。

4. 发明授权

US12135658B2 System bus transaction queue reallocation 有权
公开(公告)号：US12135658B2
公开(公告)日：2024-11-05
申请号：US17644130
申请日：2021-12-14
申请人： Atmel Corporation
发明人： Franck Lunadier , Vincent Debout
IPC分类号： G06F13/16 , G06F13/14 , G06F13/36 , G06F13/364 , G06F13/42
CPC分类号： G06F13/1642 , G06F13/14 , G06F13/36 , G06F13/364 , G06F13/4282
摘要： A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

5. 发明申请

US20170004097A1 SYSTEM BUS TRANSACTION QUEUE REALLOCATION 审中-公开
标题翻译：系统总线交易队列重启
公开(公告)号：US20170004097A1
公开(公告)日：2017-01-05
申请号：US15265057
申请日：2016-09-14
申请人： Atmel Corporation
发明人： Franck Lunadier , Vincent Debout
IPC分类号： G06F13/16 , G06F13/42 , G06F13/364
CPC分类号： G06F13/1642 , G06F13/14 , G06F13/36 , G06F13/364 , G06F13/4282
摘要： A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.
摘要翻译：公开了一种总线架构，其提供在使用总线通信的模块上的事务队列重新分配。模块可以通过数字电子电路（例如，硬件或软件或两者的组合）来实现事务请求队列。通过组合使用事务请求重播机制的乱序系统总线协议，可以避免影响常规系统的一些总线堵塞问题。模块可以从交易请求队列中排除较不紧急的事务，以便插入更紧急事务的空间。主事件模块可以在事务处于待处理状态时动态更新事务的服务质量（QoS）值。

6. 发明授权

US09372818B2 Proactive quality of service in multi-matrix system bus 有权
标题翻译：多矩阵系统总线的主动服务质量
公开(公告)号：US09372818B2
公开(公告)日：2016-06-21
申请号：US13840681
申请日：2013-03-15
申请人： ATMEL CORPORATION
发明人： Franck Lunadier , Eric Matulik , Renaud Tiennot
IPC分类号： G06F13/00 , G06F13/368 , G06F12/00 , G06F13/14 , G06F13/38
CPC分类号： G06F13/362 , G06F13/368 , G06F13/4022 , G06F13/4068
摘要： A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a network transfer request path, a highest priority value coming from an upstream arbitration node or master that has a current bus request pending at the arbitration node. The bus system ensures that any last downstream arbitration node knows at any time which is the highest priority request pending in the network transfer request path from the masters that are competing to share the bus layer switches and arbitration nodes in the network transfer request path.
摘要翻译：公开了一种多矩阵总线系统，其通过在网络传送请求路径中通过仲裁节点尽可能快地传播来自上游仲裁节点或主机的最高优先级值来提供主动服务质量（QoS）当前总线请求在仲裁节点挂起。总线系统确保任何最后一个下行仲裁节点在任何时候都知道网络传输请求路径中等待的最高优先级请求是来自正在竞争共享总线层交换机和仲裁节点的网络传输请求路径中的主机。

7. 发明授权

US11256632B2 System bus transaction queue reallocation 有权
公开(公告)号：US11256632B2
公开(公告)日：2022-02-22
申请号：US15265057
申请日：2016-09-14
申请人： Atmel Corporation
发明人： Franck Lunadier , Vincent Debout
IPC分类号： G06F13/16 , G06F13/36 , G06F13/14 , G06F13/364 , G06F13/42
摘要： A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

8. 发明申请

US20170293523A1 MULTI-CHANNEL RAM WITH ECC FOR PARTIAL WRITES 有权
公开(公告)号：US20170293523A1
公开(公告)日：2017-10-12
申请号：US15093342
申请日：2016-04-07
申请人： Atmel Corporation
发明人： Franck Lunadier
IPC分类号： G06F11/10 , G06F3/06 , G11C29/52
CPC分类号： G11C29/52 , G06F3/0619 , G06F3/064 , G06F3/0644 , G06F3/0659 , G06F3/0679 , G06F11/1048
摘要： Systems, methods, circuits and computer-readable mediums for multi-channel RAM system with error-correcting code (ECC) protection for partial writes are provided. In one aspect, a method includes accessing a plurality of bursts of partial data units from a plurality of respective bus ports, forming a plurality of memory addresses for a plurality of memory channels by interleaving addresses from the plurality of bus ports, and performing read-modify-write (RMW) error-correcting code (ECC) processes to write partial data units from the plurality of bursts into memory portions corresponding to the formed memory addresses in the plurality of memory channels.

9. 发明授权

US09898362B2 Multi-channel RAM with ECC for partial writes 有权
公开(公告)号：US09898362B2
公开(公告)日：2018-02-20
申请号：US15093342
申请日：2016-04-07
申请人： Atmel Corporation
发明人： Franck Lunadier
IPC分类号： G06F11/10 , G11C29/52 , G06F3/06
CPC分类号： G11C29/52 , G06F3/0619 , G06F3/064 , G06F3/0644 , G06F3/0659 , G06F3/0679 , G06F11/1048
摘要： Systems, methods, circuits and computer-readable mediums for multi-channel RAM system with error-correcting code (ECC) protection for partial writes are provided. In one aspect, a method includes accessing a plurality of bursts of partial data units from a plurality of respective bus ports, forming a plurality of memory addresses for a plurality of memory channels by interleaving addresses from the plurality of bus ports, and performing read-modify-write (RMW) error-correcting code (ECC) processes to write partial data units from the plurality of bursts into memory portions corresponding to the formed memory addresses in the plurality of memory channels.

10. 发明授权

US09471524B2 System bus transaction queue reallocation 有权
标题翻译：系统总线事务队列重新分配
公开(公告)号：US09471524B2
公开(公告)日：2016-10-18
申请号：US14100225
申请日：2013-12-09
申请人： Atmel Corporation
发明人： Franck Lunadier , Vincent Debout
IPC分类号： G06F13/14 , G06F13/36 , G06F13/364
CPC分类号： G06F13/1642 , G06F13/14 , G06F13/36 , G06F13/364 , G06F13/4282
摘要： A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.
摘要翻译：公开了一种总线架构，其提供在使用总线通信的模块上的事务队列重新分配。模块可以通过数字电子电路（例如，硬件或软件或两者的组合）来实现事务请求队列。通过组合使用事务请求重播机制的乱序系统总线协议，可以避免影响常规系统的一些总线堵塞问题。模块可以从交易请求队列中排除较不紧急的事务，以便插入更紧急事务的空间。主事件模块可以在事务处于待处理状态时动态更新事务的服务质量（QoS）值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式