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1. 发明授权

US07776624B2 Method for improving semiconductor surfaces 失效
标题翻译：改善半导体表面的方法
公开(公告)号：US07776624B2
公开(公告)日：2010-08-17
申请号：US12168945
申请日：2008-07-08
申请人： Ashima B. Chakravarti , Judson Robert Holt , Jeremy John Kempisty , Suk Hoon Ku , Woo-Hyeong Lee , Amlan Majumdar , Ryan Matthew Mitchell , Renee Tong Mo , Zhibin Ren , Dinkar Singh
发明人： Ashima B. Chakravarti , Judson Robert Holt , Jeremy John Kempisty , Suk Hoon Ku , Woo-Hyeong Lee , Amlan Majumdar , Ryan Matthew Mitchell , Renee Tong Mo , Zhibin Ren , Dinkar Singh
IPC分类号： H01L21/00
CPC分类号： H01L21/02532 , H01L21/02658 , H01L21/02664 , H01L21/302 , H01L21/30604 , Y10S438/947 , Y10S438/977
摘要： A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atomic percent of a first semiconductor material in the first semiconductor layer is equal to a substrate atomic percent of the substrate semiconductor material in the semiconductor substrate.
摘要翻译：半导体制造方法。该方法包括提供半导体衬底，其中半导体衬底包括半导体材料。接下来，去除半导体衬底的顶部。接下来，在半导体基板上外延生长第一半导体层，其中第一半导体层中的第一半导体材料的第一原子百分比等于半导体衬底中的衬底半导体材料的衬底原子百分比。

2. 发明申请

US20100009524A1 METHOD FOR IMPROVING SEMICONDUCTOR SURFACES 失效
标题翻译：改善半导体表面的方法
公开(公告)号：US20100009524A1
公开(公告)日：2010-01-14
申请号：US12168945
申请日：2008-07-08
申请人： Ashima B. Chakravarti , Judson Robert Holt , Jeremy John Kempisty , Suk Hoon Ku , Woo-Hyeong Lee , Amlan Majumdar , Ryan Matthew Mitchell , Renee Tong Mo , Zhibin Ren , Dinkar Singh
发明人： Ashima B. Chakravarti , Judson Robert Holt , Jeremy John Kempisty , Suk Hoon Ku , Woo-Hyeong Lee , Amlan Majumdar , Ryan Matthew Mitchell , Renee Tong Mo , Zhibin Ren , Dinkar Singh
IPC分类号： H01L21/20
CPC分类号： H01L21/02532 , H01L21/02658 , H01L21/02664 , H01L21/302 , H01L21/30604 , Y10S438/947 , Y10S438/977
摘要： A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atom percent of the semiconductor material in the first semiconductor layer is equal to a certain atom percent of the semiconductor material in the semiconductor substrate.
摘要翻译：半导体制造方法。该方法包括提供半导体衬底，其中半导体衬底包括半导体材料。接下来，去除半导体衬底的顶部。接下来，在半导体衬底上外延生长第一半导体层，其中第一半导体层中的半导体材料的第一原子百分数等于半导体衬底中半导体材料的一定原子百分数。

3. 发明授权

US07993995B2 Metal-gated MOSFET devices having scaled gate stack thickness including gettering species in a buried oxide 有权
标题翻译：金属门控MOSFET器件具有缩放的栅堆叠厚度，包括掩埋氧化物中的吸杂物质
公开(公告)号：US07993995B2
公开(公告)日：2011-08-09
申请号：US12652428
申请日：2010-01-05
申请人： Amlan Majumdar , Renee Tong Mo , Zhibin Ren , Jeffrey Sleight
发明人： Amlan Majumdar , Renee Tong Mo , Zhibin Ren , Jeffrey Sleight
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/78606 , H01L29/4908 , H01L29/6653 , H01L29/66628 , H01L29/66772 , H01L29/78603 , H01L29/78621
摘要： Metal-oxide semiconductor field effect transistor (MOSFET) devices having metal gate stacks and techniques for improving performance thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate having a buried oxide layer at least a portion of which is configured to serve as a primary background oxygen getterer of the device; and a gate stack separated from the substrate by an interfacial oxide layer. The gate stack comprises a high-K layer over the interfacial oxide layer; and a metal gate layer over the high-K layer.
摘要翻译：提供了具有金属栅叠层的金属氧化物半导体场效应晶体管（MOSFET）器件和用于提高其性能的技术。一方面，提供一种金属氧化物半导体器件，其包括具有掩埋氧化物层的衬底，其中至少一部分被配置为用作器件的主要背景氧吸收器; 以及通过界面氧化物层与衬底分离的栅极叠层。栅叠层包括在界面氧化物层上的高K层; 以及高K层上的金属栅极层。

4. 发明申请

US20090108352A1 Metal-Gated MOSFET Devices Having Scaled Gate Stack Thickness 失效
标题翻译：具有栅极堆叠厚度的金属门极MOSFET器件
公开(公告)号：US20090108352A1
公开(公告)日：2009-04-30
申请号：US11931033
申请日：2007-10-31
申请人： Amlan Majumdar , Renee Tong Mo , Zhibin Ren , Jeffrey Sleight
发明人： Amlan Majumdar , Renee Tong Mo , Zhibin Ren , Jeffrey Sleight
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78606 , H01L29/4908 , H01L29/6653 , H01L29/66628 , H01L29/66772 , H01L29/78603 , H01L29/78621
摘要： Metal-oxide semiconductor field effect transistor (MOSFET) devices having metal gate stacks and techniques for improving performance thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate having a buried oxide layer at least a portion of which is configured to serve as a primary background oxygen getterer of the device; and a gate stack separated from the substrate by an interfacial oxide layer. The gate stack comprises a high-K layer over the interfacial oxide layer; and a metal gate layer over the high-K layer.
摘要翻译：提供了具有金属栅叠层的金属氧化物半导体场效应晶体管（MOSFET）器件和用于提高其性能的技术。一方面，提供一种金属氧化物半导体器件，其包括具有掩埋氧化物层的衬底，其中至少一部分被配置为用作器件的主要背景氧吸收器; 以及通过界面氧化物层与衬底分离的栅极叠层。栅叠层包括在界面氧化物层上的高K层; 以及高K层上的金属栅极层。

5. 发明申请

US20100140707A1 Metal-Gated MOSFET Devices Having Scaled Gate Stack Thickness 有权
标题翻译：具有栅极堆叠厚度的金属门极MOSFET器件
公开(公告)号：US20100140707A1
公开(公告)日：2010-06-10
申请号：US12652428
申请日：2010-01-05
申请人： Amlan Majumdar , Renee Tong Mo , Zhibin Ren , Jeffrey Sleight
发明人： Amlan Majumdar , Renee Tong Mo , Zhibin Ren , Jeffrey Sleight
IPC分类号： H01L29/786
CPC分类号： H01L29/78606 , H01L29/4908 , H01L29/6653 , H01L29/66628 , H01L29/66772 , H01L29/78603 , H01L29/78621
摘要： Metal-oxide semiconductor field effect transistor (MOSFET) devices having metal gate stacks and techniques for improving performance thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate having a buried oxide layer at least a portion of which is configured to serve as a primary background oxygen getterer of the device; and a gate stack separated from the substrate by an interfacial oxide layer. The gate stack comprises a high-K layer over the interfacial oxide layer; and a metal gate layer over the high-K layer.
摘要翻译：提供了具有金属栅叠层的金属氧化物半导体场效应晶体管（MOSFET）器件和用于提高其性能的技术。一方面，提供一种金属氧化物半导体器件，其包括具有掩埋氧化物层的衬底，其中至少一部分被配置为用作器件的主要背景氧吸收器; 以及通过界面氧化物层与衬底分离的栅极叠层。栅叠层包括在界面氧化物层上的高K层; 以及高K层上的金属栅极层。

6. 发明授权

US07648868B2 Metal-gated MOSFET devices having scaled gate stack thickness 失效
标题翻译：具有缩放栅堆叠厚度的金属门控MOSFET器件
公开(公告)号：US07648868B2
公开(公告)日：2010-01-19
申请号：US11931033
申请日：2007-10-31
申请人： Amlan Majumdar , Renee Tong Mo , Zhibin Ren , Jeffrey Sleight
发明人： Amlan Majumdar , Renee Tong Mo , Zhibin Ren , Jeffrey Sleight
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/78606 , H01L29/4908 , H01L29/6653 , H01L29/66628 , H01L29/66772 , H01L29/78603 , H01L29/78621
摘要： Metal-oxide semiconductor field effect transistor (MOSFET) devices having metal gate stacks and techniques for improving performance thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate having a buried oxide layer at least a portion of which is configured to serve as a primary background oxygen getterer of the device; and a gate stack separated from the substrate by an interfacial oxide layer. The gate stack comprises a high-K layer over the interfacial oxide layer; and a metal gate layer over the high-K layer.
摘要翻译：提供了具有金属栅叠层的金属氧化物半导体场效应晶体管（MOSFET）器件和用于提高其性能的技术。一方面，提供一种金属氧化物半导体器件，其包括具有掩埋氧化物层的衬底，其中至少一部分被配置为用作器件的主要背景氧吸收器; 以及通过界面氧化物层与衬底分离的栅极叠层。栅叠层包括在界面氧化物层上的高K层; 以及高K层上的金属栅极层。

7. 发明授权

US07767579B2 Protection of SiGe during etch and clean operations 失效
标题翻译：在蚀刻和清洁操作期间保护SiGe
公开(公告)号：US07767579B2
公开(公告)日：2010-08-03
申请号：US11954802
申请日：2007-12-12
申请人： Ashima B Chakravarti , Zhijiong Luo , Renee Tong Mo , Shreesh Narasimha , Katsunori Onishi
发明人： Ashima B Chakravarti , Zhijiong Luo , Renee Tong Mo , Shreesh Narasimha , Katsunori Onishi
IPC分类号： H01L21/44 , H01L21/31 , H01L21/469
CPC分类号： H01L21/823807 , H01L21/02233 , H01L21/02252 , H01L21/31658 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method of making a semiconductor device includes forming a transistor structure having one of an embedded epitaxial stressed material in a source and drain region and a stressed channel and well, subjecting the transistor structure to plasma oxidation, and removing spacer material from the transistor structure.
摘要翻译：制造半导体器件的方法包括形成在源极和漏极区域中具有嵌入式外延应力材料之一的晶体管结构以及受应力的沟道和阱，对晶体管结构进行等离子体氧化，以及从晶体管结构去除间隔物材料。

8. 发明申请

US20100224940A1 Partially and Fully Silicided Gate Stacks 有权
标题翻译：部分和全硅酸盐堆叠
公开(公告)号：US20100224940A1
公开(公告)日：2010-09-09
申请号：US12782388
申请日：2010-05-18
申请人： Leland Chang , Renee Tong Mo , Jeffrey W. Sleight
发明人： Leland Chang , Renee Tong Mo , Jeffrey W. Sleight
IPC分类号： H01L27/092
CPC分类号： H01L21/823835 , H01L21/28052 , H01L21/28097 , H01L21/823842 , H01L29/4933 , H01L29/4975
摘要： Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal gate layer; a first NFET gate stack silicon layer over the NFET gate stack metal gate layer; a second NFET gate stack silicon layer over a side of the first NFET gate stack silicon layer opposite the NFET gate stack metal gate layer, wherein an interface is defined between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer; and an NFET gate stack silicide region that extends through the interface between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer.
摘要翻译：提供了金属氧化物半导体（MOS）器件及其制造技术。一方面，提供一种金属氧化物半导体器件，其包括：衬底; 以及至少一个在衬底上具有栅极堆叠的n沟道场效应晶体管（NFET）。 NFET栅极堆叠包括NFET栅极叠层金属栅极层; 在NFET栅极堆叠金属栅极层上的第一NFET栅极叠层硅层; 在所述第一NFET栅极叠层硅层的与所述NFET栅极堆叠金属栅极层相对的一侧上的第二NFET栅极堆叠硅层，其中在所述第一NFET栅极堆叠硅层和所述第二NFET栅极堆叠硅层之间限定界面; 以及延伸穿过第一NFET栅极堆叠硅层和第二NFET栅极堆叠硅层之间的界面的NFET栅极堆叠硅化物区域。

9. 发明授权

US07960795B2 Partially and fully silicided gate stacks 有权
标题翻译：部分和完全硅化栅极堆叠
公开(公告)号：US07960795B2
公开(公告)日：2011-06-14
申请号：US12782388
申请日：2010-05-18
申请人： Leland Chang , Renee Tong Mo , Jeffrey W. Sleight
发明人： Leland Chang , Renee Tong Mo , Jeffrey W. Sleight
IPC分类号： H01L21/70 , H01L21/311
CPC分类号： H01L21/823835 , H01L21/28052 , H01L21/28097 , H01L21/823842 , H01L29/4933 , H01L29/4975
摘要： Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal gate layer; a first NFET gate stack silicon layer over the NFET gate stack metal gate layer; a second NFET gate stack silicon layer over a side of the first NFET gate stack silicon layer opposite the NFET gate stack metal gate layer, wherein an interface is defined between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer; and an NFET gate stack silicide region that extends through the interface between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer.
摘要翻译：提供了金属氧化物半导体（MOS）器件及其制造技术。一方面，提供一种金属氧化物半导体器件，其包括：衬底; 以及至少一个在衬底上具有栅极堆叠的n沟道场效应晶体管（NFET）。 NFET栅极堆叠包括NFET栅极叠层金属栅极层; 在NFET栅极堆叠金属栅极层上的第一NFET栅极叠层硅层; 在所述第一NFET栅极叠层硅层的与所述NFET栅极堆叠金属栅极层相对的一侧上的第二NFET栅极堆叠硅层，其中在所述第一NFET栅极堆叠硅层和所述第二NFET栅极堆叠硅层之间限定界面; 以及延伸穿过第一NFET栅极堆叠硅层和第二NFET栅极堆叠硅层之间的界面的NFET栅极堆叠硅化物区域。

10. 发明授权

US07785952B2 Partially and fully silicided gate stacks 失效
标题翻译：部分和完全硅化栅极堆叠
公开(公告)号：US07785952B2
公开(公告)日：2010-08-31
申请号：US11873219
申请日：2007-10-16
申请人： Leland Chang , Renee Tong Mo , Jeffrey W. Sleight
发明人： Leland Chang , Renee Tong Mo , Jeffrey W. Sleight
IPC分类号： H01L21/8238 , H01L21/3205
CPC分类号： H01L21/823835 , H01L21/28052 , H01L21/28097 , H01L21/823842 , H01L29/4933 , H01L29/4975
摘要： Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal gate layer; a first NFET gate stack silicon layer over the NFET gate stack metal gate layer; a second NFET gate stack silicon layer over a side of the first NFET gate stack silicon layer opposite the NFET gate stack metal gate layer, wherein an interface is defined between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer; and an NFET gate stack silicide region that extends through the interface between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer.
摘要翻译：提供了金属氧化物半导体（MOS）器件及其制造技术。一方面，提供一种金属氧化物半导体器件，其包括：衬底; 以及至少一个在衬底上具有栅极堆叠的n沟道场效应晶体管（NFET）。 NFET栅极堆叠包括NFET栅极叠层金属栅极层; 在NFET栅极堆叠金属栅极层上的第一NFET栅极叠层硅层; 在所述第一NFET栅极叠层硅层的与所述NFET栅极堆叠金属栅极层相对的一侧上的第二NFET栅极堆叠硅层，其中在所述第一NFET栅极堆叠硅层和所述第二NFET栅极堆叠硅层之间限定界面; 以及延伸穿过第一NFET栅极堆叠硅层和第二NFET栅极堆叠硅层之间的界面的NFET栅极堆叠硅化物区域。

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