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1. 发明授权

US07776624B2 Method for improving semiconductor surfaces 失效
标题翻译：改善半导体表面的方法
公开(公告)号：US07776624B2
公开(公告)日：2010-08-17
申请号：US12168945
申请日：2008-07-08
申请人： Ashima B. Chakravarti , Judson Robert Holt , Jeremy John Kempisty , Suk Hoon Ku , Woo-Hyeong Lee , Amlan Majumdar , Ryan Matthew Mitchell , Renee Tong Mo , Zhibin Ren , Dinkar Singh
发明人： Ashima B. Chakravarti , Judson Robert Holt , Jeremy John Kempisty , Suk Hoon Ku , Woo-Hyeong Lee , Amlan Majumdar , Ryan Matthew Mitchell , Renee Tong Mo , Zhibin Ren , Dinkar Singh
IPC分类号： H01L21/00
CPC分类号： H01L21/02532 , H01L21/02658 , H01L21/02664 , H01L21/302 , H01L21/30604 , Y10S438/947 , Y10S438/977
摘要： A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atomic percent of a first semiconductor material in the first semiconductor layer is equal to a substrate atomic percent of the substrate semiconductor material in the semiconductor substrate.
摘要翻译：半导体制造方法。该方法包括提供半导体衬底，其中半导体衬底包括半导体材料。接下来，去除半导体衬底的顶部。接下来，在半导体基板上外延生长第一半导体层，其中第一半导体层中的第一半导体材料的第一原子百分比等于半导体衬底中的衬底半导体材料的衬底原子百分比。

2. 发明申请

US20100009524A1 METHOD FOR IMPROVING SEMICONDUCTOR SURFACES 失效
标题翻译：改善半导体表面的方法
公开(公告)号：US20100009524A1
公开(公告)日：2010-01-14
申请号：US12168945
申请日：2008-07-08
申请人： Ashima B. Chakravarti , Judson Robert Holt , Jeremy John Kempisty , Suk Hoon Ku , Woo-Hyeong Lee , Amlan Majumdar , Ryan Matthew Mitchell , Renee Tong Mo , Zhibin Ren , Dinkar Singh
发明人： Ashima B. Chakravarti , Judson Robert Holt , Jeremy John Kempisty , Suk Hoon Ku , Woo-Hyeong Lee , Amlan Majumdar , Ryan Matthew Mitchell , Renee Tong Mo , Zhibin Ren , Dinkar Singh
IPC分类号： H01L21/20
CPC分类号： H01L21/02532 , H01L21/02658 , H01L21/02664 , H01L21/302 , H01L21/30604 , Y10S438/947 , Y10S438/977
摘要： A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atom percent of the semiconductor material in the first semiconductor layer is equal to a certain atom percent of the semiconductor material in the semiconductor substrate.
摘要翻译：半导体制造方法。该方法包括提供半导体衬底，其中半导体衬底包括半导体材料。接下来，去除半导体衬底的顶部。接下来，在半导体衬底上外延生长第一半导体层，其中第一半导体层中的半导体材料的第一原子百分数等于半导体衬底中半导体材料的一定原子百分数。

3. 发明申请

US20090289305A1 ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBEDDED SIGE PFET EXTENSION 审中-公开
标题翻译：具有增加的外延源和漏极和嵌入式信号扩展的超薄SOI CMOS
公开(公告)号：US20090289305A1
公开(公告)日：2009-11-26
申请号：US12535306
申请日：2009-08-04
申请人： Amlan Majumdar , Gen Pei , Zhibin Ren , Dinkar Singh , Jeffrey W. Sleight
发明人： Amlan Majumdar , Gen Pei , Zhibin Ren , Dinkar Singh , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L29/786
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1203 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.
摘要翻译：通过将嵌入的pFET SiGe扩展与升高的源极/漏极区域集成来提高超薄硅上氧化物（UTSOI）FET器件中的沟道载流子迁移率的方法。该方法包括选择性地生长pFET区域中的嵌入式SiGe（eSiGe）扩展，并在CMOS上形成无应力的升高的Si或SiGe源极/漏极（RSD）区域。 eSiGe延伸区增强了pFET通道中的空穴迁移率，并降低了pFET延伸中的电阻。无应变的升高的源极/漏极区域减小了两个UTSOI pFET和nFET中的接触电阻。

4. 发明申请

US20080217686A1 ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBEDDED SIGE PFET EXTENSION 审中-公开
标题翻译：具有增加的外延源和漏极和嵌入式信号扩展的超薄SOI CMOS
公开(公告)号：US20080217686A1
公开(公告)日：2008-09-11
申请号：US11684122
申请日：2007-03-09
申请人： Amlan Majumdar , Gen Pei , Zhibin Ren , Dinkar Singh , Jeffrey W. Sleight
发明人： Amlan Majumdar , Gen Pei , Zhibin Ren , Dinkar Singh , Jeffrey W. Sleight
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1203 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.
摘要翻译：通过将嵌入的pFET SiGe扩展与升高的源极/漏极区域集成来提高超薄硅上氧化物（UTSOI）FET器件中的沟道载流子迁移率的方法。该方法包括选择性地生长pFET区域中的嵌入式SiGe（eSiGe）扩展，并在CMOS上形成无应力的升高的Si或SiGe源极/漏极（RSD）区域。 eSiGe延伸区增强了pFET通道中的空穴迁移率，并降低了pFET延伸中的电阻。无应变的升高的源极/漏极区域减小了两个UTSOI pFET和nFET中的接触电阻。

5. 发明申请

US20110165739A1 ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBEDDED SIGE PFET EXTENSION 有权
标题翻译：具有增加的外延源和漏极和嵌入式信号扩展的超薄SOI CMOS
公开(公告)号：US20110165739A1
公开(公告)日：2011-07-07
申请号：US13052702
申请日：2011-03-21
申请人： Amlan Majumdar , Gen Pei , Zhibin Ren , Dinkar Singh , Jeffrey W. Sleight
发明人： Amlan Majumdar , Gen Pei , Zhibin Ren , Dinkar Singh , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1203 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.
摘要翻译：通过将嵌入的pFET SiGe扩展与升高的源极/漏极区域集成来提高超薄硅上氧化物（UTSOI）FET器件中的沟道载流子迁移率的方法。该方法包括选择性地生长pFET区域中的嵌入式SiGe（eSiGe）扩展，并在CMOS上形成无应力的升高的Si或SiGe源极/漏极（RSD）区域。 eSiGe延伸区增强了pFET通道中的空穴迁移率，并降低了pFET延伸中的电阻。无应变的升高的源极/漏极区域减小了两个UTSOI pFET和nFET中的接触电阻。

6. 发明授权

US08012820B2 Ultra-thin SOI CMOS with raised epitaxial source and drain and embedded SiGe PFET extension 有权
标题翻译：具有凸起的外延源和漏极和嵌入式SiGe PFET扩展的超薄SOI CMOS
公开(公告)号：US08012820B2
公开(公告)日：2011-09-06
申请号：US13052702
申请日：2011-03-21
申请人： Amlan Majumdar , Gen Pei , Zhibin Ren , Dinkar Singh , Jeffrey W. Sleight
发明人： Amlan Majumdar , Gen Pei , Zhibin Ren , Dinkar Singh , Jeffrey W. Sleight
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1203 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.
摘要翻译：通过将嵌入的pFET SiGe扩展与升高的源极/漏极区域集成来提高超薄硅上氧化物（UTSOI）FET器件中的沟道载流子迁移率的方法。该方法包括选择性地生长pFET区域中的嵌入式SiGe（eSiGe）扩展，并在CMOS上形成无应力的升高的Si或SiGe源极/漏极（RSD）区域。 eSiGe延伸区增强了pFET通道中的空穴迁移率，并降低了pFET延伸中的电阻。无应变的升高的源极/漏极区域减小了两个UTSOI pFET和nFET中的接触电阻。

7. 发明申请

US20070184619A1 Selective incorporation of charge for transistor channels 有权
标题翻译：选择性地并入晶体管通道的电荷
公开(公告)号：US20070184619A1
公开(公告)日：2007-08-09
申请号：US11346662
申请日：2006-02-03
申请人： John Hergenrother , Zhibin Ren , Dinkar Singh , Jeffrey Sleight
发明人： John Hergenrother , Zhibin Ren , Dinkar Singh , Jeffrey Sleight
IPC分类号： H01L21/336
CPC分类号： H01L21/28097 , H01L21/26506 , H01L21/28185 , H01L21/7624 , H01L29/4975 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.
摘要翻译：用于选择性地将电荷放置到栅极堆叠中的器件和方法包括形成包括邻近晶体管沟道和栅极导体的栅极电介质的栅极堆叠，并形成用于晶体管操作的掺杂区域。在掺杂区域和栅极叠层上沉积富含钝化元素的层，并且从所选择的晶体管去除富含钝化元件的层。富含钝化元件的层比退火以驱动钝化元件，以增加在存在钝化元件的层的晶体管上的晶体管沟槽处或附近的电荷浓度。去除富含钝化元素的层。

8. 发明申请

US20070284654A1 METAL ALLOY LAYER OVER CONDUCTIVE REGION OF TRANSISTOR DEVICE OF DIFFERENT CONDUCTIVE MATERIAL THAN CONDUCTIVE REGION 审中-公开
标题翻译：不同导电材料与导电区域的晶体管器件导电区域的金属合金层
公开(公告)号：US20070284654A1
公开(公告)日：2007-12-13
申请号：US11422965
申请日：2006-06-08
申请人： Judith M. Rubino , James Pan , Dinkar Singh , Jonathan Smith , Anna Topol
发明人： Judith M. Rubino , James Pan , Dinkar Singh , Jonathan Smith , Anna Topol
IPC分类号： H01L29/76
CPC分类号： H01L29/78 , H01L29/7845
摘要： A transistor device and method are disclosed for reducing parasitic resistance and enhancing channel mobility using a metal alloy layer over a conductive region. A transistor device may include a conductive region such as a source, drain and/or gate including at least one first conductive material, and a metal alloy layer disposed on substantially all of a surface of the conductive region, the metal alloy layer including a second conductive material different than the at least one first conductive materials. In one embodiment, the second conductive material includes a cobalt and/or nickel alloy. The metal alloy layer provides a non-epitaxial raised source/drain (and gate) to reduce the parasitic series resistance in, for example, nFETs fabricated on UTSOI. In addition, the metal alloy layer may include a stress to enhance mobility in a channel of the transistor device. The metal alloy layer may be formed using a selective electrochemical metal deposition process such as electroless or electrolytic plating.
摘要翻译：公开了一种晶体管器件和方法，用于在导电区域上使用金属合金层降低寄生电阻并增强沟道迁移率。晶体管器件可以包括导电区域，例如包括至少一个第一导电材料的源极，漏极和/或栅极以及设置在导电区域的基本上所有表面上的金属合金层，金属合金层包括第二导电区域导电材料不同于至少一种第一导电材料。在一个实施例中，第二导电材料包括钴和/或镍合金。金属合金层提供非外延凸起的源极/漏极（和栅极），以减少例如在UTSOI上制造的nFET的寄生串联电阻。此外，金属合金层可以包括提高晶体管器件的沟道中的迁移率的应力。可以使用诸如无电镀或电解电镀的选择性电化学金属沉积工艺来形成金属合金层。

9. 发明授权

US06740535B2 Enhanced T-gate structure for modulation doped field effect transistors 有权
公开(公告)号：US06740535B2
公开(公告)日：2004-05-25
申请号：US10207352
申请日：2002-07-29
申请人： Dinkar Singh , Katherine Lynn Saenger , Vishnubhai V. Patel , Alfred Grill , Steven John Koester
发明人： Dinkar Singh , Katherine Lynn Saenger , Vishnubhai V. Patel , Alfred Grill , Steven John Koester
IPC分类号： H01L21338
CPC分类号： H01L21/28587 , H01L29/42316
摘要： A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.

10. 发明授权

US08101150B2 Control of carbon nanotube diameter using CVD or PECVD growth 有权
标题翻译：使用CVD或PECVD生长控制碳纳米管直径
公开(公告)号：US08101150B2
公开(公告)日：2012-01-24
申请号：US12483757
申请日：2009-06-12
申请人： Alfred Grill , Deborah Neumayer , Dinkar Singh
发明人： Alfred Grill , Deborah Neumayer , Dinkar Singh
IPC分类号： D01C5/00
CPC分类号： B82Y30/00 , B82Y10/00 , B82Y40/00 , C01B32/162 , C01B2202/36 , C30B25/00 , C30B25/105 , C30B29/605 , H01J9/025 , H01J2201/30469 , Y10S977/843
摘要： The diameter of carbon nanotubes grown by chemical vapor deposition is controlled independent of the catalyst size by controlling the residence time of reactive gases in the reactor.
摘要翻译：通过化学气相沉积生长的碳纳米管的直径通过控制反应性气体在反应器中的停留时间独立于催化剂的尺寸来控制。

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