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1. 发明授权

US07348914B1 Method and systems to align outputs signals of an analog-to-digital converter 有权
标题翻译：对准模拟 - 数字转换器的输出信号的方法和系统
公开(公告)号：US07348914B1
公开(公告)日：2008-03-25
申请号：US11477759
申请日：2006-06-29
申请人： Asher Hazanchuk , Ian Ing , Satwant Singh
发明人： Asher Hazanchuk , Ian Ing , Satwant Singh
IPC分类号： H03M1/12
CPC分类号： H03M1/124 , H03M1/1215
摘要： Systems and methods are disclosed herein to provide improved alignment of output signals of an analog-to-digital converter (ADC). For example, in accordance with an embodiment of the present invention, a method of aligning digital signals appearing on signal paths of a parallel data bus includes sampling the digital signals at a plurality of delay times to obtain a plurality of sample sets, wherein each sample set is associated with a corresponding delay time. A second digital signal that is misaligned with respect to a first digital signal is identified from the sample sets. The delay time required to align the second digital signal with the first digital signal is determined. The delay of the second digital signal is adjusted by the determined delay time.
摘要翻译：本文公开了系统和方法以提供模数转换器（ADC）的输出信号的改进对准。例如，根据本发明的实施例，对并行数据总线的信号路径上出现的数字信号进行对准的方法包括以多个延迟时间对数字信号进行采样以获得多个样本集，其中每个样本设置与相应的延迟时间相关联。从样本集中识别相对于第一数字信号不对准的第二数字信号。确定将第二数字信号与第一数字信号对准所需的延迟时间。第二数字信号的延迟由确定的延迟时间进行调整。

2. 发明授权

US08463832B1 Digital signal processing block architecture for programmable logic device 有权
标题翻译：用于可编程逻辑器件的数字信号处理块架构
公开(公告)号：US08463832B1
公开(公告)日：2013-06-11
申请号：US12146042
申请日：2008-06-25
申请人： Asher Hazanchuk , Ian Ing , Satwant Singh
发明人： Asher Hazanchuk , Ian Ing , Satwant Singh
IPC分类号： G06F7/38
CPC分类号： G06F7/5324 , H03K19/1732 , H03K19/1737
摘要： Various implementations of a digital signal processing (DSP) block architecture of a programmable logic device (PLD) and related methods are provided. In one example, a PLD includes a dedicated DSP block. The DSP block includes a first multiplier adapted to multiply a first plurality of input signals to provide a first plurality of product signals. The DSP block also includes a second multiplier adapted to multiply a second plurality of input signals to provide a second plurality of product signals. The DSP block further includes an arithmetic logic unit (ALU) adapted to operate on the first product signals and the second product signals received at first and second operand inputs, respectively, of the ALU to provide a plurality of output signals.
摘要翻译：提供了可编程逻辑器件（PLD）的数字信号处理（DSP）块结构的各种实施方式和相关方法。在一个示例中，PLD包括专用DSP块。 DSP块包括适于乘以第一多个输入信号以提供第一多个乘积信号的第一乘法器。 DSP块还包括适于乘以第二多个输入信号以提供第二多个乘积信号的第二乘法器。 DSP块还包括算术逻辑单元（ALU），其适于对分别在ALU的第一和第二操作数输入处接收的第一乘积信号和第二乘积信号进行操作，以提供多个输出信号。

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