专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08850232B2 Method for protecting a cryptographic module and a device having cryptographic module protection capabilities 有权
标题翻译：用于保护加密模块的方法和具有加密模块保护能力的设备
公开(公告)号：US08850232B2
公开(公告)日：2014-09-30
申请号：US12919541
申请日：2008-03-19
申请人： Michael Priel , Asaf Ashkenazi , Dan Kuzmin , Anton Rozen
发明人： Michael Priel , Asaf Ashkenazi , Dan Kuzmin , Anton Rozen
IPC分类号： G06F12/14 , G08B29/00 , G06F21/55 , G06F21/86
CPC分类号： G06F21/558 , G06F21/554 , G06F21/755 , G06F21/86
摘要： A device and a method for protecting a cryptographic module of which the method includes: estimating a functionality of a circuit that is adapted to malfunction when a physical parameter has a first value different from a nominal parameter value at which the cryptographic module functions correctly. The cryptographic module malfunctions when the physical parameter has a second value different from the nominal parameter value and a difference between the first value and the nominal parameter value being smaller than a difference between the second value and the nominal parameter value. A cryptographic module protective measure is applied if estimating that the circuit malfunctions.
摘要翻译：一种用于保护密码模块的设备和方法，该方法包括：当物理参数具有与加密模块正常工作的标称参数值不同的第一值时，估计适于故障的电路的功能。当物理参数具有与标称参数值不同的第二值并且第一值和标称参数值之间的差小于第二值和标称参数值之间的差时，加密模块发生故障。如果估计电路发生故障，则应用加密模块保护措施。

2. 发明授权

US07941716B2 Method for race prevention and a device having race prevention capabilities 有权
标题翻译：防止竞赛的方法和具有防守能力的装置
公开(公告)号：US07941716B2
公开(公告)日：2011-05-10
申请号：US11909394
申请日：2005-03-23
申请人： Michael Priel , Dan Kuzmin , Anton Rozen
发明人： Michael Priel , Dan Kuzmin , Anton Rozen
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G01R31/318541 , G01R31/318536 , H03K3/0375
摘要： A method for race prevention includes: selectively providing data or scan data to a input latching logic, activating the input latching logic for a first scan mode activation period, introducing a substantial time shift between the first scan mode activation period and a second scan mode activation period, and activating a output latching logic, connected to the input latching logic for a second scan mode activation period. A device having race prevention capabilities includes: an interface logic, a input latching logic, a output latching logic and a control logic. The interface logic is adapted to selectively provide data or scan data to the input latching logic. The control logic is adapted to introduce a substantial time difference between an end point of a first scan mode activation period of the input latching logic and a start point of a second scan mode activation period of the output latching logic.
摘要翻译：一种防止竞赛的方法包括：选择性地向输入锁存逻辑提供数据或扫描数据，在第一扫描模式激活期间激活输入锁存逻辑，在第一扫描模式激活期和第二扫描模式激活之间引入实质的时间偏移并且激活输出锁存逻辑，连接到输入锁存逻辑用于第二扫描模式激活周期。具有防止竞争能力的装置包括：接口逻辑，输入锁存逻辑，输出锁存逻辑和控制逻辑。接口逻辑适于选择性地向输入锁存逻辑提供数据或扫描数据。控制逻辑适于在输入锁存逻辑的第一扫描模式激活周期的终点与输出锁存逻辑的第二扫描模式激活周期的起始点之间引入实质的时间差。

3. 发明申请

US20140325183A1 INTEGRATED CIRCUIT DEVICE, ASYMMETRIC MULTI-CORE PROCESSING MODULE, ELECTRONIC DEVICE AND METHOD OF MANAGING EXECUTION OF COMPUTER PROGRAM CODE THEREFOR 审中-公开
标题翻译：集成电路设备，不对称多核处理模块，电子设备及其计算机程序代码的执行方法
公开(公告)号：US20140325183A1
公开(公告)日：2014-10-30
申请号：US14358053
申请日：2011-11-28
申请人： Anton Rozen , Dan Kuzmin , Michael Priel , Leonid Smolyansky
发明人： Anton Rozen , Dan Kuzmin , Michael Priel , Leonid Smolyansky
IPC分类号： G06F15/76
CPC分类号： G06F15/76 , G06F9/5083 , G06F9/5094 , G06F2015/765 , Y02D10/22
摘要： An asymmetric multi-core processing module is described. The asymmetric multi-core processing module comprises at least one processing core of a first type, at least one processing core of at least one further type, and at least one core identifier configuration component. The at least one core identifier configuration component is arranged to enable dynamic configuration of a value of a core identifier of at least one of the processing cores of the first and at least one further types.
摘要翻译：描述了一种非对称多核处理模块。非对称多核处理模块包括至少一个第一类型的处理核心，至少一个另外类型的至少一个处理核心和至少一个核心标识符配置组件。至少一个核心标识符配置组件被布置成使得能够动态地配置第一和至少一个其它类型的至少一个处理核心的核心标识符的值。

4. 发明授权

US08402288B2 Apparatus and method for controlling voltage and frequency using multiple reference circuits 有权
标题翻译：使用多个参考电路控制电压和频率的装置和方法
公开(公告)号：US08402288B2
公开(公告)日：2013-03-19
申请号：US11719015
申请日：2004-11-10
申请人： Anton Rozen , Michael Priel , Dan Kuzmin
发明人： Anton Rozen , Michael Priel , Dan Kuzmin
IPC分类号： G06F1/00 , G06F17/50 , G05F1/10 , G05F3/02 , G06G7/48 , G06G7/62
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system. The method comprises: providing at least one reference circuit representative of a behavior of at least one estimated circuit, whereas the at least one estimated circuit includes transistors of multiple types; supplying at least one input signal to at least one reference circuits and monitoring a behavior of the at least one reference circuit one or more reference circuit; determining a characteristic of at least one output signal provided to the at least one estimated circuit; and providing at least one output signal to one or more estimated circuitsThe apparatus includes at least one reference circuit representative of a behavior of at least one estimated circuit, whereas the at least one estimated circuit includes transistors of multiple types; and monitoring circuitry adapted to monitor a behavior of at least one reference circuit and to determine a characteristic of at least one output signal provided to the at least one estimated circuit.
摘要翻译：一种用于控制提供给系统的电压电平和时钟信号频率的方法和装置。该方法包括：提供代表至少一个估计电路的行为的至少一个参考电路，而至少一个估计电路包括多种类型的晶体管; 向至少一个参考电路提供至少一个输入信号并监视所述至少一个参考电路的行为一个或多个参考电路; 确定提供给所述至少一个估计电路的至少一个输出信号的特性; 并且向一个或多个估计电路提供至少一个输出信号。所述装置包括表示至少一个估计电路的行为的至少一个参考电路，而所述至少一个估计电路包括多种类型的晶体管; 以及监视电路，其适于监视至少一个参考电路的行为并且确定提供给所述至少一个估计电路的至少一个输出信号的特性。

5. 发明申请

US20130007431A1 INTEGRATED CIRCUIT DEVICE, SIGNAL PROCESSING SYSTEM, ELECTRONIC DEVICE AND METHOD THEREFOR 有权
标题翻译：集成电路装置，信号处理系统，电子装置及其方法
公开(公告)号：US20130007431A1
公开(公告)日：2013-01-03
申请号：US13582769
申请日：2010-03-22
申请人： Michael Priel , Dan Kuzmin , Anton Rozen
发明人： Michael Priel , Dan Kuzmin , Anton Rozen
IPC分类号： G06F9/00 , G06F1/32
CPC分类号： H04W52/0261 , G06F1/32 , G06F9/00 , Y02D70/00
摘要： An integrated circuit device comprises a signal processing system having at least one first signal processing module fabricated by way of a first production process; and at least one second signal processing module fabricated by way of a second production process, wherein the second production process is different to the first production process. The signal processing system further comprises a signal processing management module arranged to: determine a desired system performance of the integrated circuit device; determine at least one operating condition of the signal processing system; and configure a signal processing operating mode of the signal processing system based at least partly on: the determined desired system performance; the at least one determined operating condition; and at least one of the first production process and the second production process.
摘要翻译：集成电路装置包括信号处理系统，该信号处理系统具有通过第一生产过程制造的至少一个第一信号处理模块; 以及通过第二生产过程制造的至少一个第二信号处理模块，其中第二生产过程与第一生产过程不同。信号处理系统还包括信号处理管理模块，其被布置成：确定集成电路装置的期望的系统性能; 确定信号处理系统的至少一个操作条件; 并且至少部分地基于：确定的期望系统性能来配置所述信号处理系统的信号处理操作模式; 所述至少一个确定的操作条件; 以及第一生产过程和第二生产过程中的至少一个。

6. 发明授权

US08060324B2 Device and a method for estimating transistor parameter variations 有权
标题翻译：器件和估计晶体管参数变化的方法
公开(公告)号：US08060324B2
公开(公告)日：2011-11-15
申请号：US12162179
申请日：2006-02-01
申请人： Michael Priel , Dan Kuzmin , Anton Rozen
发明人： Michael Priel , Dan Kuzmin , Anton Rozen
IPC分类号： G01R11/073 , G01R11/20 , G01R19/165 , G06F11/07
CPC分类号： G01R31/27 , G01R31/2882
摘要： A method and a device for estimating parameter variations of transistors that belong to the same circuit. The method includes: providing the first circuit; providing a test circuit adapted to perform a first function and a stacked test circuit adapted to perform a second function that substantially equals the first function; wherein the test circuit, the stacked test circuit and the first circuit are processed under substantially the same processing conditions; determining a relationship between a parameter of the test circuit and a parameter of the stacked test circuit; and estimating parameter variations of transistors that belong to the first circuit in response to the determined relationship.
摘要翻译：一种用于估计属于相同电路的晶体管的参数变化的方法和装置。该方法包括：提供第一电路; 提供适于执行第一功能的测试电路和适于执行基本上等于所述第一功能的第二功能的堆叠测试电路; 其中所述测试电路，所述堆叠测试电路和所述第一电路在基本相同的处理条件下进行处理; 确定所述测试电路的参数与所述堆叠测试电路的参数之间的关系; 以及响应于所确定的关系估计属于所述第一电路的晶体管的参数变化。

7. 发明申请

US20100060342A1 METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES 有权
标题翻译：降低功率的方法和具有降低功率的装置
公开(公告)号：US20100060342A1
公开(公告)日：2010-03-11
申请号：US12208145
申请日：2008-09-10
申请人： Anton Rozen , Dan Kuzmin , Michael Priel
发明人： Anton Rozen , Dan Kuzmin , Michael Priel
IPC分类号： H03L5/02 , H03K17/00
CPC分类号： H03K19/0016 , H03K2017/0806
摘要： A device that includes: (i) an evaluated circuit; (ii) a leakage current dependent oscillator configured to generate an oscillating signal that has an oscillating frequency that represents a leakage current of the evaluated circuit; (iii) a switching current dependent oscillator configured to generate an oscillating signal that has an oscillating frequency that represents a switching induced current of the evaluated circuit; (iv) a power reduction module that is configured to: (a) compare between an oscillation frequency of the leakage current dependent oscillator and an oscillation frequency of the switching current dependent oscillator, to provide a current comparison result; (b) select a power reduction technique out of a dynamic voltage and frequency scaling technique and a power gating technique in view of the current comparison result; and (c) apply the selected power reduction technique.
摘要翻译：一种装置，包括：（i）评估电路; （ii）漏电流相关振荡器，被配置为产生具有表示所述评估电路的漏电流的振荡频率的振荡信号; （iii）开关电流相关振荡器，被配置为产生具有表示所述评估电路的开关感应电流的振荡频率的振荡信号; （iv）功率降低模块，被配置为：（a）将所述与漏电流相关的振荡器的振荡频率与所述开关电流相关振荡器的振荡频率进行比较，以提供当前比较结果; （b）考虑到当前的比较结果，从动态电压和频率缩放技术和电源门控技术中选择功率降低技术; 和（c）应用所选择的功率降低技术。

8. 发明申请

US20080209248A1 Method For Power Reduction And A Device Having Power Reduction Capabilities 有权
标题翻译：降低功耗的方法和具有降低功耗的器件
公开(公告)号：US20080209248A1
公开(公告)日：2008-08-28
申请号：US11914079
申请日：2005-05-11
申请人： Michael Priel , Dan Kuzmin , Anton Rozen , Leonid Smolyanski
发明人： Michael Priel , Dan Kuzmin , Anton Rozen , Leonid Smolyanski
IPC分类号： G06F1/28
CPC分类号： G06F1/3225 , G06F1/3275 , G06F1/3287 , G06F12/0804 , G06F12/0864 , G06F2212/1028 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A method for power reduction, the method includes determining whether to power down the at least portion of the component in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power mode, and selectively providing power to at least a portion of a component of an integrated circuit during a low power mode. A device having power reduction capabilities, the device includes power switching circuitry adapted to selectively provide power to at least a portion of a component of the device during a low power mode, and a power management circuitry adapted to determine whether to power down at least the portion of the component during a low power mode in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power.
摘要翻译：一种用于功率降低的方法，所述方法包括：响应于所估计的功率增益与在所述低电平期间对所述部件的至少部分断电而导致的估计功率损耗之间的关系来确定是否对所述部件的所述至少部分进行断电功率模式，并且在低功率模式期间选择性地向集成电路的部件的至少一部分供电。一种具有功率降低功能的装置，该装置包括功率开关电路，其适于在低功率模式期间选择性地向装置的部件的至少一部分提供功率，以及功率管理电路，其适于确定是否至少断电响应于估计的功率增益与在低功率期间对部件的至少部分断电而导致的估计的功率损耗之间的关系，在低功率模式期间部件的部分。

9. 发明授权

US07227366B2 Device and a method for biasing a transistor that is connected to a power converter 有权
标题翻译：用于偏置连接到功率转换器的晶体管的装置和方法
公开(公告)号：US07227366B2
公开(公告)日：2007-06-05
申请号：US10955219
申请日：2004-09-30
申请人： Anton Rozen , Dan Kuzmin , Michael Priel
发明人： Anton Rozen , Dan Kuzmin , Michael Priel
IPC分类号： G01R35/00 , H03K3/01
CPC分类号： G01R31/2621
摘要： Biasing a transistor connected to a voltage converter, the method includes: (i) providing at least one bias voltage to at least one well of at least one transistor of a test circuitry; (ii) measuring at least one parameter of a test circuitry representative of at least one characteristic of the transistor and of at least one characteristic of the voltage converter; (iii) altering at least one bias voltage and repeating the stages of providing and measuring until a predefined control criteria is fulfilled; and (iv) providing a voltage bias to a well of the transistor in response to the measurements.
摘要翻译：对连接到电压转换器的晶体管进行偏置，该方法包括：（i）向测试电路的至少一个晶体管的至少一个阱提供至少一个偏置电压; （ii）测量表示所述晶体管的至少一个特性和所述电压转换器的至少一个特性的测试电路的至少一个参数; （iii）改变至少一个偏置电压并重复提供和测量的阶段，直到满足预定义的控制标准; 以及（iv）响应于测量，向晶体管的阱提供电压偏置。

10. 发明授权

US09462556B2 Integrated circuit device, signal processing system, electronic device and method for configuring a signal processing operating mode 有权
标题翻译：集成电路装置，信号处理系统，用于配置信号处理操作模式的电子装置和方法
公开(公告)号：US09462556B2
公开(公告)日：2016-10-04
申请号：US13582769
申请日：2010-03-22
申请人： Michael Priel , Dan Kuzmin , Anton Rozen
发明人： Michael Priel , Dan Kuzmin , Anton Rozen
IPC分类号： G06F9/00 , G06F1/32 , H04W52/02
CPC分类号： H04W52/0261 , G06F1/32 , G06F9/00 , Y02D70/00
摘要： An integrated circuit device comprises a signal processing system having at least one first signal processing module fabricated by way of a first production process; and at least one second signal processing module fabricated by way of a second production process, wherein the second production process is different to the first production process. The signal processing system further comprises a signal processing management module arranged to: determine a desired system performance of the integrated circuit device; determine at least one operating condition of the signal processing system; and configure a signal processing operating mode of the signal processing system based at least partly on: the determined desired system performance; the at least one determined operating condition; and at least one of the first production process and the second production process.
摘要翻译：集成电路装置包括信号处理系统，该信号处理系统具有通过第一生产过程制造的至少一个第一信号处理模块; 以及通过第二生产过程制造的至少一个第二信号处理模块，其中第二生产过程与第一生产过程不同。信号处理系统还包括信号处理管理模块，其被布置成：确定集成电路装置的期望的系统性能; 确定信号处理系统的至少一个操作条件; 并且至少部分地基于：确定的期望系统性能来配置所述信号处理系统的信号处理操作模式; 所述至少一个确定的操作条件; 以及第一生产过程和第二生产过程中的至少一个。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式