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1. 发明申请

US20080188089A1 METHOD FOR REDUCING TOP NOTCHING EFFECTS IN PRE-DOPED GATE STRUCTURES 审中-公开
标题翻译：用于减少前浇口结构中顶部止点效应的方法
公开(公告)号：US20080188089A1
公开(公告)日：2008-08-07
申请号：US11671668
申请日：2007-02-06
申请人： Anthony I. Chou , Sadanand V. Deshpande , Renee T. Mo , Shreesh Narasimha , Katsunori Onishi , Dominic Schepis
发明人： Anthony I. Chou , Sadanand V. Deshpande , Renee T. Mo , Shreesh Narasimha , Katsunori Onishi , Dominic Schepis
IPC分类号： H01L21/31
CPC分类号： H01L21/32105 , H01L21/28035 , H01L21/28247
摘要： A method for reducing top notching effects in pre-doped gate structures includes subjecting an etched, pre-doped gate stack structure to a re-oxidation process, the re-oxidation process comprising a radical assisted re-oxidation process so as to result in the formation of an oxide layer over vertical sidewall and horizontal top surfaces of the etched gate stack structure. The resulting oxide layer has a substantially uniform thickness independent of grain boundary orientations of the gate stack structure and independent of the concentration and location of dopant material present therein.
摘要翻译：用于减少预掺杂栅极结构中的顶部切口效应的方法包括将经蚀刻的预掺杂栅极堆叠结构进行再氧化处理，所述再氧化工艺包括自由基辅助再氧化工艺，以便导致在蚀刻的栅堆叠结构的垂直侧壁和水平顶表面上形成氧化物层。所得到的氧化物层具有与栅极堆叠结构的晶界取向无关的基本均匀的厚度，而与其中存在的掺杂剂材料的浓度和位置无关。

2. 发明授权

US07932144B2 Semiconductor structure and method of forming the structure 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US07932144B2
公开(公告)日：2011-04-26
申请号：US12685027
申请日：2010-01-11
申请人： Yaocheng Liu , Shreesh Narasimha , Katsunori Onishi , Kern Rim
发明人： Yaocheng Liu , Shreesh Narasimha , Katsunori Onishi , Kern Rim
IPC分类号： H01L21/8234
CPC分类号： H01L27/1203 , H01L21/26506 , H01L21/26513 , H01L21/28247 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/1045 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.
摘要翻译：公开了具有完全包含在非晶化区域内和具有无碳栅电极的硅碳S / D区域的n-FET结构的实施方案。在非晶化区域内含有碳，确保在再结晶后所有碳都是取代的，以最大限度地增加通道区域上施加的拉伸应力。在碳注入期间，栅极堆叠被封盖，从而基本上消除了碳进入栅极堆叠并降低栅极多晶硅的导电性和/或损坏栅极氧化物的风险。因此，可以更深地形成碳注入区域。完全非晶化然后再结晶的深S / D碳植入物在n-FET沟道区域上提供更大的拉伸应力，以进一步优化电子迁移率。此外，在n型掺杂剂处理期间，栅电极未被封装，因此栅电极中的n型掺杂剂剂量可以至少大于S / D区域中的剂量。

3. 发明授权

US07767579B2 Protection of SiGe during etch and clean operations 失效
标题翻译：在蚀刻和清洁操作期间保护SiGe
公开(公告)号：US07767579B2
公开(公告)日：2010-08-03
申请号：US11954802
申请日：2007-12-12
申请人： Ashima B Chakravarti , Zhijiong Luo , Renee Tong Mo , Shreesh Narasimha , Katsunori Onishi
发明人： Ashima B Chakravarti , Zhijiong Luo , Renee Tong Mo , Shreesh Narasimha , Katsunori Onishi
IPC分类号： H01L21/44 , H01L21/31 , H01L21/469
CPC分类号： H01L21/823807 , H01L21/02233 , H01L21/02252 , H01L21/31658 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method of making a semiconductor device includes forming a transistor structure having one of an embedded epitaxial stressed material in a source and drain region and a stressed channel and well, subjecting the transistor structure to plasma oxidation, and removing spacer material from the transistor structure.
摘要翻译：制造半导体器件的方法包括形成在源极和漏极区域中具有嵌入式外延应力材料之一的晶体管结构以及受应力的沟道和阱，对晶体管结构进行等离子体氧化，以及从晶体管结构去除间隔物材料。

4. 发明申请

US20080191243A1 SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE STRUCTURE 失效
标题翻译：半导体结构和形成结构的方法
公开(公告)号：US20080191243A1
公开(公告)日：2008-08-14
申请号：US11672599
申请日：2007-02-08
申请人： Yaocheng Liu , Shreesh Narasimha , Katsunori Onishi , Kern Rim
发明人： Yaocheng Liu , Shreesh Narasimha , Katsunori Onishi , Kern Rim
IPC分类号： H01L27/092 , H01L29/778 , H01L21/8238 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/26506 , H01L21/26513 , H01L21/28247 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/1045 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.
摘要翻译：公开了具有完全包含在非晶化区域内和具有无碳栅电极的硅碳S / D区域的n-FET结构的实施方案。在非晶化区域内含有碳，确保在再结晶后所有碳都是取代的，以最大限度地增加通道区域上施加的拉伸应力。在碳注入期间，栅极堆叠被封盖，从而基本上消除了碳进入栅极堆叠并降低栅极多晶硅的导电性和/或损坏栅极氧化物的风险。因此，可以更深地形成碳注入区域。完全非晶化然后再结晶的深S / D碳植入物在n-FET沟道区域上提供更大的拉伸应力，以进一步优化电子迁移率。此外，在n型掺杂剂处理期间，栅电极未被封装，因此栅电极中的n型掺杂剂剂量可以至少大于S / D区域中的剂量。

5. 发明授权

US07714358B2 Semiconductor structure and method of forming the structure 失效
标题翻译：半导体结构及其形成方法
公开(公告)号：US07714358B2
公开(公告)日：2010-05-11
申请号：US11672599
申请日：2007-02-08
申请人： Yaocheng Liu , Shreesh Narasimha , Katsunori Onishi , Kern Rim
发明人： Yaocheng Liu , Shreesh Narasimha , Katsunori Onishi , Kern Rim
IPC分类号： H01L27/092
CPC分类号： H01L27/1203 , H01L21/26506 , H01L21/26513 , H01L21/28247 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/1045 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.
摘要翻译：公开了具有完全包含在非晶化区域内和具有无碳栅电极的硅碳S / D区域的n-FET结构的实施方案。在非晶化区域内含有碳，确保在再结晶后所有碳都是取代的，以最大限度地增加通道区域上施加的拉伸应力。在碳注入期间，栅极堆叠被封盖，从而基本上消除了碳进入栅极堆叠并降低栅极多晶硅的导电性和/或损坏栅极氧化物的风险。因此，可以更深地形成碳注入区域。完全非晶化然后再结晶的深S / D碳植入物在n-FET沟道区域上提供更大的拉伸应力，以进一步优化电子迁移率。此外，在n型掺杂剂处理期间，栅电极未被封装，因此栅电极中的n型掺杂剂剂量可以至少大于S / D区域中的剂量。

6. 发明申请

US20100112766A1 SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：半导体结构和形成结构的方法
公开(公告)号：US20100112766A1
公开(公告)日：2010-05-06
申请号：US12685027
申请日：2010-01-11
申请人： Yaocheng Liu , Shreesh Narasimha , Katsunori Onishi , Kern Rim
发明人： Yaocheng Liu , Shreesh Narasimha , Katsunori Onishi , Kern Rim
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/26506 , H01L21/26513 , H01L21/28247 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/1045 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.
摘要翻译：公开了具有完全包含在非晶化区域内和具有无碳栅电极的硅碳S / D区域的n-FET结构的实施方案。在非晶化区域内含有碳，确保在再结晶后所有碳都是取代的，以最大限度地增加通道区域上施加的拉伸应力。在碳注入期间，栅极堆叠被封盖，从而基本上消除了碳进入栅极堆叠并降低栅极多晶硅的导电性和/或损坏栅极氧化物的风险。因此，可以更深地形成碳注入区域。完全非晶化然后再结晶的深S / D碳植入物在n-FET沟道区域上提供更大的拉伸应力，以进一步优化电子迁移率。此外，在n型掺杂剂处理期间，栅电极未被封装，因此栅电极中的n型掺杂剂剂量可以至少大于S / D区域中的剂量。

7. 发明申请

US20090146223A1 PROCESS AND METHOD TO LOWER CONTACT RESISTANCE 审中-公开
标题翻译：降低接触电阻的方法和方法
公开(公告)号：US20090146223A1
公开(公告)日：2009-06-11
申请号：US11950574
申请日：2007-12-05
申请人： Sameer H. Jain , Shreesh Narasimha , Karen A. Nummy , Katsunori Onishi , Viorel C. Ontalus , Jang H. Sim
发明人： Sameer H. Jain , Shreesh Narasimha , Karen A. Nummy , Katsunori Onishi , Viorel C. Ontalus , Jang H. Sim
IPC分类号： H01L29/94 , H01L21/8236
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/268 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/808 , H01L29/812
摘要： A method removes the spacers from the sides of a transistor gate stack, and after the spacers are removed, the method implants an additional impurity into surface regions of the substrate not protected by the gate conductor (or alternatively just amorphizes these surface regions, without adding more impurity). The method then performs a laser anneal on the additional impurity (to activate the additional impurity) or amorphized regions (to recrystallize the amorphized regions). After this, permanent spacers are formed on the sidewalls of the gate conductor. Then, the surface regions of the substrate not protected by the gate conductor and the permanent spacers are silicided, to create silicide source/drain regions. This forms the silicide regions in the additional impurity or in the recrystallized amorphized regions to reduce the source/drain resistance by improving the active dopant concentration at the silicon-silicide interface.
摘要翻译：一种方法从晶体管栅极堆叠的侧面去除间隔物，并且在间隔物被去除之后，该方法将不附加栅极导体保护的衬底的另外的杂质注入到衬底的表面区域中（或者只是将这些表面区域非晶化，而不添加更多的杂质）。然后，该方法对另外的杂质（以激活附加杂质）或非晶化区域（使非晶化区域重结晶）进行激光退火。之后，在栅极导体的侧壁上形成永久的间隔物。然后，将不被栅极导体和永久性间隔物保护的衬底的表面区域硅化，以产生硅化物源极/漏极区域。这会在附加杂质或再结晶非晶化区域中形成硅化物区域，以通过改善硅硅化物界面处的活性掺杂剂浓度来降低源/漏电阻。

8. 发明授权

US07610590B2 Optical disc apparatus 失效
标题翻译：光盘装置
公开(公告)号：US07610590B2
公开(公告)日：2009-10-27
申请号：US11593507
申请日：2006-11-07
申请人： Kazumasa Nasu , Katsunori Onishi , Takayuki Murakami , Katsuo Ichinohe , Yasuhiro Nishina , Shinya Yamaguchi , Nobuyuki Okazaki , Ryuuji Hayashi
发明人： Kazumasa Nasu , Katsunori Onishi , Takayuki Murakami , Katsuo Ichinohe , Yasuhiro Nishina , Shinya Yamaguchi , Nobuyuki Okazaki , Ryuuji Hayashi
IPC分类号： G11B17/03
CPC分类号： G11B17/056
摘要： There are provided a disc tray, a traverse unit, and a main chassis unit. The main chassis unit has a main chassis, which has, as observed when the traverse unit is in a stand-by position, a latch portion that engages with a projection portion of a sub rack and a stopper member that restricts the movement of the cam slider. The stopper member has a rotary shaft in the shape of a circular column, a lever portion which the projection portion makes contact, and a lock portion that makes contact with the cam slider and thereby restricts the sliding movement of the cam slider.
摘要翻译：提供了光盘托盘，横动单元和主机箱单元。主底盘单元具有主底盘，当横移单元处于待机位置时，其具有与副齿条的突出部分接合的闩锁部分和限制凸轮的移动的止动构件滑块止动构件具有圆柱形的旋转轴，突出部接触的杆部和与凸轮滑块接触的锁定部，从而限制凸轮滑块的滑动。

9. 发明申请

US20050118764A1 Forming gate oxides having multiple thicknesses 失效
标题翻译：形成具有多个厚度的栅极氧化物
公开(公告)号：US20050118764A1
公开(公告)日：2005-06-02
申请号：US10724483
申请日：2003-11-28
申请人： Anthony Chou , Michael Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul Kirsch , Byoung Lee , Katsunori Onishi , Heemyoung Park , Kristen Scheer , Akihisa Sekiguchi
发明人： Anthony Chou , Michael Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul Kirsch , Byoung Lee , Katsunori Onishi , Heemyoung Park , Kristen Scheer , Akihisa Sekiguchi
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/84
CPC分类号： H01L21/823462 , H01L21/823857
摘要： Gate oxides having different thicknesses are formed on a semiconductor substrate by forming a first gate oxide on the top surface of the substrate, forming a sacrificial hard mask over a selected area of the first gate oxide; and then forming a second gate oxide. A first poly layer may be formed on the first gate oxide, under the hard mask. After the hard mask is removed, a second poly layer may be formed over the second gate oxide and over the first poly layer. This enables the use of high-k dielectric materials, and the first gate oxide can be thinner than the second gate oxide.
摘要翻译：通过在衬底的顶表面上形成第一栅极氧化物，在半导体衬底上形成具有不同厚度的栅极氧化物，在第一栅极氧化物的选定区域上形成牺牲性硬掩模; 然后形成第二栅极氧化物。可以在硬掩模下的第一栅极氧化物上形成第一多晶硅层。在去除硬掩模之后，可以在第二栅极氧化物之上和第一多晶硅层上形成第二多晶硅层。这使得能够使用高k电介质材料，并且第一栅极氧化物可以比第二栅极氧化物薄。

10. 发明授权

US06057979A Magnetic tape cassette with fail-safe inserting apparatus 失效
标题翻译：带有故障安全插入装置的磁带盒
公开(公告)号：US06057979A
公开(公告)日：2000-05-02
申请号：US964254
申请日：1997-11-04
申请人： Kunio Sawai , Hiroshi Hamahata , Shigeru Kaneko , Katsunori Onishi
发明人： Kunio Sawai , Hiroshi Hamahata , Shigeru Kaneko , Katsunori Onishi
IPC分类号： G11B15/675 , G11B15/00
CPC分类号： G11B15/67547
摘要： A magnetic tape apparatus having a bearer formed so as to be reciprocatable in the front-rear direction between a cassette insertion position and a cassette mount position on a chassis for inserting a tape cassette, and a rotating cam provided on the chassis for driving the bearer through an interlocking mechanism with a clutch. In the magnetic tape apparatus, the clutch is turned off to release the interlocking mechanism between the bearer and the rotating cam when the bearer is advanced from the cassette mount position to the cassette insertion position, while the clutch is turned on to establish the interlock between the bearer and the rotating cam when the bearer is retreated from the cassette insertion position to the cassette mount position.
摘要翻译：一种磁带装置，其具有形成为能够在前后方向上在盒插入位置和用于插入带盒的底盘上的盒安装位置之间往复运动的承载件，以及设置在底盘上用于驱动承载件的旋转凸轮通过与离合器的联锁机构。在磁带装置中，当承载体从盒安装位置前进到盒插入位置时，离合器被关闭以释放承载件和旋转凸轮之间的互锁机构，同时离合器打开以建立互锁当承载件从盒插入位置退回到盒安装位置时，承载件和旋转凸轮。

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