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1. 发明申请

US20130127044A1 MICRO SURFACE MOUNT DEVICE PACKAGING 审中-公开
标题翻译：微表面装置包装
公开(公告)号：US20130127044A1
公开(公告)日：2013-05-23
申请号：US13303073
申请日：2011-11-22
申请人： Anindya Poddar , Tao Feng , Will K. Wong
发明人： Anindya Poddar , Tao Feng , Will K. Wong
IPC分类号： H01L23/488 , H01L21/78
CPC分类号： H01L24/97 , H01L21/561 , H01L21/568 , H01L23/13 , H01L23/145 , H01L23/3114 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L2224/12105 , H01L2224/13022 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/12042 , H01L2924/15153 , H01L2924/157 , H01L2924/15724 , H01L2924/1579 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： A variety of improved approaches for packaging integrated circuits are described. In one described approach, a multiplicity of die cavities are formed in a plastic carrier. In some preferred embodiments, the die cavities are formed by laser ablation. A multiplicity of dice are placed on the carrier, with each die being placed in an associated die cavity. Each of the dice preferably has a multiplicity of I/O bumps formed thereon. An encapsulant is applied over the carrier to form an encapsulant layer that covers the dice and fills portions of the cavities that are not occupied by the dice. In some preferred embodiments, the encapsulant is an epoxy material applied by screen printing and the dice are not physically attached to the carrier prior to the application of the encapsulant. In these embodiments, the epoxy encapsulant serves to secure the dice to the carrier.
摘要翻译：描述了用于封装集成电路的各种改进方法。在一种所描述的方法中，在塑料载体中形成多个模腔。在一些优选实施例中，模腔通过激光烧蚀形成。将多个骰子放置在载体上，每个模具被放置在相关的模腔中。每个骰子优选地具有形成在其上的多个I / O凸块。将密封剂施加在载体上以形成覆盖骰子并填充未被骰子占据的空腔的部分的密封剂层。在一些优选的实施方案中，密封剂是通过丝网印刷施加的环氧材料，并且在施加密封剂之前，骰子不物理附着到载体上。在这些实施例中，环氧树脂密封剂用于将骰子固定到载体上。

2. 发明授权

US08450151B1 Micro surface mount device packaging 有权
标题翻译：微表面贴装装置包装
公开(公告)号：US08450151B1
公开(公告)日：2013-05-28
申请号：US13303053
申请日：2011-11-22
申请人： Anindya Poddar , Tao Feng , Will K. Wong
发明人： Anindya Poddar , Tao Feng , Will K. Wong
IPC分类号： H01L23/08 , H01L23/488 , H01L23/28
CPC分类号： H01L24/19 , H01L21/561 , H01L21/568 , H01L23/13 , H01L23/145 , H01L23/3114 , H01L23/49816 , H01L23/5389 , H01L24/97 , H01L2223/6677 , H01L2224/04105 , H01L2224/12105 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/12042 , H01L2924/15153 , H01L2224/83 , H01L2924/00
摘要： A variety of improved approaches for packaging integrated circuits are described. In one described approach, a multiplicity of dice are mounted on a carrier (e.g., a plastic carrier). Each die has a plurality of wire bonded contact studs secured to its associated I/O pads. An encapsulant is applied over the carrier to cover the dice and at least portions of the contact studs to form an encapsulant carrier structure. After the encapsulant has been applied, a first surface of the encapsulant and the contact studs are ground such that exposed portions of the contact studs are smooth and substantially co-planar with the encapsulant. In some embodiments, a redistribution layer is formed over the encapsulant carrier structure and solder bumps are attached to the redistribution layer. A contact encapsulant layer is applied over the encapsulant carrier structure to provide extra mechanical support for the resulting packages.
摘要翻译：描述了用于封装集成电路的各种改进方法。在所描述的方法中，多个骰子安装在载体（例如，塑料载体）上。每个管芯具有固定到其相关联的I / O焊盘的多个引线接合柱塞。在载体上施加密封剂以覆盖骰子和至少部分接触柱以形成密封剂载体结构。在施加了密封剂之后，密封剂的第一表面和接触柱被研磨，使得接触柱的暴露部分与密封剂平滑并且基本上共面。在一些实施例中，在密封剂载体结构上方形成再分配层，并且焊料凸块附着到再分配层。接触密封剂层施加在密封剂载体结构上以为所得到的包装提供额外的机械支撑。

3. 发明申请

US20130127043A1 MICRO SURFACE MOUNT DEVICE PACKAGING 有权
标题翻译：微表面装置包装
公开(公告)号：US20130127043A1
公开(公告)日：2013-05-23
申请号：US13303053
申请日：2011-11-22
申请人： Anindya Poddar , Tao Feng , Will K. Wong
发明人： Anindya Poddar , Tao Feng , Will K. Wong
IPC分类号： H01L23/488 , H01L21/78
CPC分类号： H01L24/19 , H01L21/561 , H01L21/568 , H01L23/13 , H01L23/145 , H01L23/3114 , H01L23/49816 , H01L23/5389 , H01L24/97 , H01L2223/6677 , H01L2224/04105 , H01L2224/12105 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/12042 , H01L2924/15153 , H01L2224/83 , H01L2924/00
摘要： A variety of improved approaches for packaging integrated circuits are described. In one described approach, a multiplicity of dice are mounted on a carrier (e.g., a plastic carrier). Each die has a plurality of wire bonded contact studs secured to its associated I/O pads. An encapsulant is applied over the carrier to cover the dice and at least portions of the contact studs to form an encapsulant carrier structure. After the encapsulant has been applied, a first surface of the encapsulant and the contact studs are ground such that exposed portions of the contact studs are smooth and substantially co-planar with the encapsulant. In some embodiments, a redistribution layer is formed over the encapsulant carrier structure and solder bumps are attached to the redistribution layer. A contact encapsulant layer is applied over the encapsulant carrier structure to provide extra mechanical support for the resulting packages.
摘要翻译：描述了用于封装集成电路的各种改进方法。在所描述的方法中，多个骰子安装在载体（例如，塑料载体）上。每个管芯具有固定到其相关联的I / O焊盘的多个引线接合柱塞。在载体上施加密封剂以覆盖骰子和至少部分接触柱以形成密封剂载体结构。在施加了密封剂之后，密封剂的第一表面和接触柱被研磨，使得接触柱的暴露部分与密封剂平滑并且基本上共面。在一些实施例中，在密封剂载体结构上方形成再分配层，并且焊料凸块附着到再分配层。接触密封剂层施加在密封剂载体结构上以为所得到的包装提供额外的机械支撑。

4. 发明授权

US09163035B2 Melonine bisindole compounds, pharmaceutical compositions, preparation method and use thereof 有权
标题翻译：甜菜双吲哚化合物，药物组合物，其制备方法和用途
公开(公告)号：US09163035B2
公开(公告)日：2015-10-20
申请号：US13508277
申请日：2010-11-04
申请人： Xiaodong Luo , Tao Feng , Yan Li , Yuanyuan Wang , Xianghai Cai , Yaping Liu
发明人： Xiaodong Luo , Tao Feng , Yan Li , Yuanyuan Wang , Xianghai Cai , Yaping Liu
IPC分类号： C07D519/04 , A61K31/4375 , A61K31/475 , A61K36/24 , C07D519/00
CPC分类号： C07D519/04 , A61K31/4375 , A61K31/475 , A61K36/24 , C07D519/00
摘要： The present invention relates to pharmaceutical technical field, to melonine bisindole compounds, pharmaceutical compositions thereof, and preparation methods thereof. Specifically, the present invention relates to melonine bisindole compounds of Formula I, pharmaceutically acceptable salts thereof, pharmaceutical compositions comprising the compounds or pharmaceutically acceptable salts thereof. The present invention further relates to method for preparing the melonine bisindole compounds of Formula I or pharmaceutically acceptable salts thereof, and the use of the melonine bisindole compounds of Formula I or pharmaceutically acceptable salts thereof in the manufacture of a medicament for the treatment or prophylaxis of cancers.
摘要翻译：本发明涉及药用技术领域，甜瓜双吲哚化合物及其药物组合物及其制备方法。具体地，本发明涉及式I的甜瓜双吲哚化合物，其药学上可接受的盐，包含该化合物或其药学上可接受的盐的药物组合物。本发明还涉及制备式I的甜菜双吲哚化合物或其药学上可接受的盐的方法，以及式I的甜瓜双吲哚化合物或其药学上可接受的盐在制备用于治疗或预防癌症

5. 发明授权

US08866267B2 Semiconductor device with substrate-side exposed device-side electrode and method of fabrication 有权
标题翻译：具有基板侧暴露的器件侧电极的半导体器件及其制造方法
公开(公告)号：US08866267B2
公开(公告)日：2014-10-21
申请号：US12790773
申请日：2010-05-28
申请人： Tao Feng , Anup Bhalla
发明人： Tao Feng , Anup Bhalla
IPC分类号： H01L29/40 , H01L29/78 , H01L29/423 , H01L29/66 , H01L23/48 , H01L29/06 , H01L23/00 , H01L29/417
CPC分类号： H01L23/49844 , H01L23/481 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L29/0657 , H01L29/41741 , H01L29/42372 , H01L29/66734 , H01L29/781 , H01L29/7813 , H01L29/7827 , H01L2224/04042 , H01L2224/0557 , H01L2224/05571 , H01L2224/0603 , H01L2224/06051 , H01L2224/06102 , H01L2224/29006 , H01L2224/29007 , H01L2224/32245 , H01L2224/45014 , H01L2224/48247 , H01L2224/48463 , H01L2224/48465 , H01L2224/49107 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/05552 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side electrode (SSE) and a windowed substrate-side passivation (SSPV) atop SSE can be included. The SSPV defines an area of SSE for spreading solder material during device packaging. A device-side passivation (DSPV) beneath thus covering the device-side of SEDE can be included. A DSE can also include an extended support ledge, stacked below an SEDE, for structurally supporting it during post-wafer processing packaging. The projected footprint of extended support ledge onto the major SCS plane can essentially enclose the correspondingly projected footprint of SEDE.
摘要翻译：公开了一种具有基板侧暴露的器件侧电极（SEDE）的半导体器件。半导体器件在器件侧具有器件侧，衬底侧和半导体器件区（SDR）的半导体衬底（SCS）。形成器件侧电极（DSE）用于器件操作。通过衬底沟槽（TST）延伸通过SCS，达到DSE将其变成SEDE。 SEDE可以通过TST通过导电互连器相互连接。可以包括在SSE上面的衬底侧电极（SSE）和窗口化的衬底侧钝化（SSPV）。 SSPV定义了在设备封装期间扩展焊料材料的SSE区域。可以包括下面覆盖SEDE的器件侧的器件侧钝化（DSPV）。 DSE还可以包括在SEDE下面堆叠的扩展支撑凸缘，用于在晶片间加工包装期间对其进行结构支持。延伸支撑突出到主SCS平面上的预计占地面积基本上可以包围SEDE相应的预计占地面积。

6. 发明授权

US08466060B2 Stackable power MOSFET, power MOSFET stack, and process of manufacture 有权
标题翻译：可堆叠功率MOSFET，功率MOSFET堆栈和制造工艺
公开(公告)号：US08466060B2
公开(公告)日：2013-06-18
申请号：US12772048
申请日：2010-04-30
申请人： Tao Feng
发明人： Tao Feng
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L23/3107 , H01L21/6836 , H01L23/481 , H01L23/4824 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/40 , H01L24/48 , H01L24/94 , H01L25/074 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/05552 , H01L2224/05554 , H01L2224/0557 , H01L2224/0603 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/32245 , H01L2224/40095 , H01L2224/40247 , H01L2224/48227 , H01L2224/48247 , H01L2224/81894 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2225/0651 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12041 , H01L2924/12044 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/37099
摘要： A thin and stackable power MOSFET (SP-MOSFET) and method are proposed. The SVP-MOSFET includes semiconductor substrate with bottom drain metal layer. Formed atop the semiconductor substrate are trenched gate regions and source-body regions. A patterned gate metal layer and source-body metal layer respectively contact trenched gate regions and source-body regions. At least one of through substrate drain via (TSDV), through substrate gate via (TSGV), through substrate source via (TSSV) is provided. The TSDV, formed through semiconductor substrate and in contact with drain metal layer, has top drain contacting pad and bottom drain contacting pad for making top and bottom contacts thereto. Similarly the TSGV, formed through semiconductor substrate and in contact with gate metal layer, has top gate contacting pad and bottom gate contacting pad. Likewise the TSSV, formed through semiconductor substrate and in contact with source-body metal layer, has top source contacting pad and bottom source contacting pad.
摘要翻译：提出了一种薄型和可堆叠功率MOSFET（SP-MOSFET）和方法。 SVP-MOSFET包括具有底部漏极金属层的半导体衬底。形成在半导体衬底顶部的是沟槽栅区和源体区。图案化栅极金属层和源体金属层分别接触沟槽栅极区域和源极体区域。提供贯穿衬底漏极通孔（TSDV），衬底栅极通孔（TSGV），衬底源极通孔（TSSV）中的至少一个。通过半导体衬底形成并与漏极金属层接触的TSDV具有顶部漏极接触焊盘和底部漏极接触焊盘，用于与其接触。类似地，通过半导体衬底形成并与栅极金属层接触的TSGV具有顶栅接触焊盘和底栅接触焊盘。同样地，通过半导体衬底形成并与源体金属层接触的TSSV具有顶部源接触焊盘和底部源接触焊盘。

7. 发明授权

US08461004B2 Configuration of high-voltage semiconductor power device to achieve three dimensional charge coupling 有权
标题翻译：配置高压半导体功率器件实现三维电荷耦合
公开(公告)号：US08461004B2
公开(公告)日：2013-06-11
申请号：US13066373
申请日：2011-04-12
申请人： François Hébert , Tao Feng
发明人： François Hébert , Tao Feng
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L29/0653 , H01L29/66712 , H01L29/7395 , H01L29/7803 , H01L29/861 , H01L29/872
摘要： This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path.
摘要翻译：本发明公开了一种半导体器件，其包括顶部区域和底部区域，其中间区域设置在所述顶部区域和所述底部区域之间，并具有穿过所述中间区域的可控电流通路。所述半导体器件还包括沟槽，该沟槽在从所述顶部区域延伸穿过所述中间区域朝向所述底部区域的侧壁上被填充有绝缘层，其中所述沟槽包括随机均匀分布的纳米结节，作为与下面的漏极区域接触的电荷岛用于与中间区域电耦合的沟槽，用于通过电流路径连续均匀地分配电压降。

8. 发明申请

US20120235306A1 Virtually Substrate-less Composite Power Semiconductor Device 有权
标题翻译：几何无基板复合功率半导体器件
公开(公告)号：US20120235306A1
公开(公告)日：2012-09-20
申请号：US13488424
申请日：2012-06-04
申请人： Tao Feng , Yueh-Se Ho
发明人： Tao Feng , Yueh-Se Ho
IPC分类号： H01L23/48
CPC分类号： H01L21/561 , H01L23/142 , H01L23/3114 , H01L23/49827 , H01L24/29 , H01L24/92 , H01L2224/29101 , H01L2224/2919 , H01L2224/8385 , H01L2224/9202 , H01L2224/94 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
摘要： A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness TPSD. The FDC has patterned back-face carrier metallizations contacting the front-face device metallization pads, patterned front-face carrier metallization pads and numerous parallelly connected through-carrier conductive vias respectively connecting the back-face carrier metallizations to the front-face carrier metallization pads. The FDC thickness TFDC is large enough to provide structural rigidity to the VSLCPSD. The diminishing thickness TPSD effects a low back substrate resistance and the through-carrier conductive vias effect a low front-face contact resistance to the front-face device metallization pads.
摘要翻译：公开了一种实际上无衬底的复合功率半导体器件（VSLCPSD）和方法。 VSLCPSD具有功率半导体器件（PSD），由载体材料制成的正面器件载体（FDC）和中间键合层（IBL）。载体和IBL材料都可以是导电的或不导电的。 PSD具有后衬底部分，具有图案化前面装置金属化焊盘的前半导体器件部分和实际上减小的厚度TPSD。 FDC具有接触前表面器件金属化焊盘，图案化前面载体金属化焊盘和多个并联连接的贯穿载体导电通孔的图案化背面载体金属化，其分别将背面载体金属化物连接到前面载体金属化焊盘。 FDC厚度TFDC足够大以向VSLCPSD提供结构刚度。厚度减小的TPSD会影响背面的底层电阻，并且贯穿载体的导电通孔会对前面装置的金属化焊盘产生低的前端接触电阻。

9. 发明申请

US20120161307A1 CHIP SCALE SURFACE MOUNTED SEMICONDUCTOR DEVICE PACKAGE AND PROCESS OF MANUFACTURE 有权
标题翻译：芯片尺寸表面安装半导体器件封装及其制造工艺
公开(公告)号：US20120161307A1
公开(公告)日：2012-06-28
申请号：US13409625
申请日：2012-03-01
申请人： Tao Feng
发明人： Tao Feng
IPC分类号： H01L23/52
CPC分类号： H01L29/0657 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/29 , H01L24/32 , H01L24/94 , H01L2224/02371 , H01L2224/03011 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0362 , H01L2224/05548 , H01L2224/05558 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/06182 , H01L2224/08225 , H01L2224/2919 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48666 , H01L2224/48744 , H01L2224/48747 , H01L2224/48755 , H01L2224/48766 , H01L2224/83805 , H01L2224/94 , H01L2924/00014 , H01L2924/0002 , H01L2924/01322 , H01L2924/10253 , H01L2924/1306 , H01L2924/13091 , H01L2924/157 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/00 , H01L2924/01079 , H01L2924/01028 , H01L2924/01029 , H01L2924/01013 , H01L2924/01047 , H01L2224/03 , H01L2224/83 , H01L2224/48 , H01L2224/05552
摘要： A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.
摘要翻译：公开了一种半导体器件封装管芯及其制造方法。器件封装裸片可以包括具有一个或多个前电极的器件衬底，位于器件衬底的前表面上，并且电连接到靠近前表面形成在器件衬底内的一个或多个相应器件区域。背面导电层形成在器件衬底的背面上。背面导电层电连接到在器件衬底附近形成的器件区域，靠近器件衬底的后表面。一个或多个导电延伸部形成在与背导电层电接触的器件衬底的一个或多个相应的侧壁上，并且延伸到器件衬底的前表面的一部分。支撑基板结合到装置基板的背面。

10. 发明授权

US07971340B2 Planar grooved power inductor structure and method 有权
标题翻译：平面沟槽功率电感结构及方法
公开(公告)号：US07971340B2
公开(公告)日：2011-07-05
申请号：US13007551
申请日：2011-01-14
申请人： François Hébert , Tao Feng , Jun Lu
发明人： François Hébert , Tao Feng , Jun Lu
IPC分类号： H01F7/02
CPC分类号： H01F17/0033 , H01F1/344 , H01F41/046 , H01F2017/002 , Y10T29/4902
摘要： An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.
摘要翻译：电感器可以包括平面铁氧体磁芯。第一组一个或多个凹槽形成在铁氧体磁芯的第一侧。在铁氧体磁芯的第二侧形成有第二组两个或多个凹槽。第一组和第二组中的凹槽被定向成使得第一组中的每个凹槽与第二组中的两个相应的凹槽重叠。第一多个通孔在铁氧体磁芯的第一和第二侧之间通过铁氧体磁芯连通。每个通孔位于第一组中的凹槽与第二组中的凹槽重叠的位置。导电材料设置在第一和第二组沟槽和通孔中以形成电感线圈。

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