专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07161379B2 Shunted current reduction 失效
标题翻译：分流电流下降
公开(公告)号：US07161379B2
公开(公告)日：2007-01-09
申请号：US11089571
申请日：2004-04-14
申请人： Barry J. Arnold , Kevin M. Laake , Andrew R. Allen
发明人： Barry J. Arnold , Kevin M. Laake , Andrew R. Allen
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0175 , H03K5/08 , H03L5/00
CPC分类号： H04L25/0298
摘要： One disclosed method comprises drawing current from a termination voltage supply and through a termination voltage delivery network by termination circuitry in response to a first signal on one or more lines terminated by the termination circuitry, shunting current from the termination voltage supply and through the termination voltage delivery network in response to a second signal on one or more terminated lines, and helping to reduce the shunted current for extended shunting.
摘要翻译：一种公开的方法包括响应于由终端电路终止的一条或多条线路上的第一信号，通过终端电路从终端电压电源和终端电压传送网络中抽出电流，从终端电压源分流电流并通过终止电压响应于一个或多个终止线路上的第二信号，并且有助于减少用于分流的分流电流。

2. 发明授权

US07057415B2 Output buffer compensation control 有权
标题翻译：输出缓冲器补偿控制
公开(公告)号：US07057415B2
公开(公告)日：2006-06-06
申请号：US10732695
申请日：2003-12-10
申请人： Andrew R. Allen , Barry J. Arnold
发明人： Andrew R. Allen , Barry J. Arnold
IPC分类号： H03K19/175
CPC分类号： H03K19/00369
摘要： One or more characteristics of circuitry for an output buffer are identified relative to a reference a plurality of times to produce a sequence of results. One or more compensation signals for one or more output buffers are generated based on results satisfying one or more conditions.
摘要翻译：用于输出缓冲器的电路的一个或多个特性相对于参考多次被识别以产生一系列结果。基于满足一个或多个条件的结果生成一个或多个输出缓冲器的一个或多个补偿信号。

3. 发明授权

US08467489B2 Data clock recovery system and method employing delayed data clock phase shifting 有权
标题翻译：数据时钟恢复系统和采用延迟数据时钟相移的方法
公开(公告)号：US08467489B2
公开(公告)日：2013-06-18
申请号：US11210929
申请日：2005-08-24
申请人： Dacheng (Henry) Zhou , Barry J. Arnold
发明人： Dacheng (Henry) Zhou , Barry J. Arnold
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/0812 , H04L7/0025
摘要： A data clock recovery system is provided. A phase detector is configured to sample an input data stream by way of a data clock and a second clock to generate a first signal indicating whether a data clock lags or leads a preferred phase of the data clock in relation to an input data stream. A phase controller is configured to process the first signal to shift a phase of the second clock toward a second preferred phase, and to shift a phase of the data clock toward the first preferred phase after the shifting of the phase of the second clock.
摘要翻译：提供了数据时钟恢复系统。相位检测器被配置为通过数据时钟和第二时钟对输入数据流进行采样以产生指示数据时钟相对于输入数据流是滞后还是导致数据时钟的优选相位的第一信号。相位控制器被配置为处理第一信号以将第二时钟的相位移向第二优选相位，并且在第二时钟的相位移位之后将数据时钟的相位移向第一优选相位。

4. 发明授权

US06986087B2 Method and apparatus for improving testability of I/O driver/receivers 有权
标题翻译：用于提高I / O驱动器/接收器的可测试性的方法和装置
公开(公告)号：US06986087B2
公开(公告)日：2006-01-10
申请号：US10238570
申请日：2002-09-09
申请人： Kevin Laake , Navin Ghisiawan , Barry J. Arnold
发明人： Kevin Laake , Navin Ghisiawan , Barry J. Arnold
IPC分类号： G11R31/28
CPC分类号： G01R31/3185 , G01R31/31716
摘要： An embodiment of this invention provides a circuit and method for improving the testability of I/O driver/receivers. First, two separate I/O driver/receiver pads are electrically connected. A bit pattern generator in one of the I/O driver/receivers drives a bit pattern through a driver to the connected pads. The bit pattern is then driven through the receiver of a second I/O driver/receiver to a first clocked register. An identical bit pattern generator in the second I/O driver/receiver then drives an identical bit pattern into a second clocked register. A comparator compares the outputs of these two registers. If the two bit patterns don't match, the comparator signals there is a functional problem with one of the I/O driver/receivers.
摘要翻译：本发明的实施例提供了一种用于提高I / O驱动器/接收机的可测试性的电路和方法。首先，两个独立的I / O驱动器/接收器焊盘电连接。其中一个I / O驱动器/接收器中的位模式发生器通过驱动器将驱动器的位模式驱动到连接的焊盘。然后，位模式通过第二I / O驱动器/接收器的接收器被驱动到第一时钟寄存器。第二I / O驱动器/接收器中相同的位模式发生器然后将相同的位模式驱动到第二个时钟寄存器中。比较器比较这两个寄存器的输出。如果两个位模式不匹配，则比较器信号与I / O驱动器/接收器之一存在功能问题。

5. 发明授权

US5467026A Pseudo-NMOS logic circuits with negligible static current during quiescent current testing 失效
标题翻译：在静态电流测试期间具有可忽略静态电流的伪NMOS逻辑电路
公开(公告)号：US5467026A
公开(公告)日：1995-11-14
申请号：US183539
申请日：1994-01-18
申请人： Barry J. Arnold
发明人： Barry J. Arnold
IPC分类号： G01R31/30 , H03K19/00 , H03K19/0944 , H03K17/16
CPC分类号： G01R31/3004 , H03K19/0013 , H03K19/09441
摘要： A modified pseudo-nMOS logic gate for use in systems in which quiescent current testing is desired. The load transistor of each pseudo-nMOS gate is controlled by a two-input load control gate. One input of the load control gate is connected to a global test signal and the second input of the load control gate is connected to the output of the pseudo-nMOS gate. In normal operation, the global test signal is logically true, and the load control gate has no effect on the pseudo-nMOS gate. During quiescent current testing, the global test signal is logically false and the output of the load control gate is determined by the logical output of the pseudo-nMOS gate. If the output of the pseudo-nMOS gate is logically true, the load control gate has no effect on the pseudo-nMOS gate. If the output of the pseudo-nMOS gate is logically false, the load control gate turns off the load transistor so that no static current flows through the load transistor. As a result, the logical state of the pseudo-nMOS gate is preserved, but the modified gate draws negligible static current during quiescent current testing.
摘要翻译：用于需要静态电流测试的系统中的修改的伪nMOS逻辑门。每个伪nMOS门的负载晶体管由双输入负载控制门控制。负载控制门的一个输入连接到全局测试信号，负载控制门的第二个输入端连接到伪nMOS门的输出端。在正常操作中，全局测试信号在逻辑上为真，负载控制门对伪nMOS门没有影响。在静态电流测试期间，全局测试信号在逻辑上为假，并且负载控制门的输出由伪nMOS门的逻辑输出决定。如果伪nMOS门的输出逻辑上为真，则负载控制门对伪nMOS门无影响。如果伪nMOS栅极的输出逻辑上为假，则负载控制栅极关断负载晶体管，使得没有静态电流流过负载晶体管。结果，保留了伪nMOS门的逻辑状态，但是在静态电流测试期间，修改后的栅极可以忽略静态电流。

6. 发明授权

US07113000B2 Bus agent having multiple reference levels 失效
标题翻译：总线代理具有多个参考级别
公开(公告)号：US07113000B2
公开(公告)日：2006-09-26
申请号：US10732684
申请日：2003-12-10
申请人： Barry J. Arnold
发明人： Barry J. Arnold
IPC分类号： H03K19/0175
CPC分类号： G06F13/4086
摘要： An integrated circuit is configured as a selected one of a terminated and a non-terminated bus agent for terminating a bus signal line. Reference level selection logic selects one of a first and a distinct second reference level as a selected level. The integrated circuit compares the bus signal line with the selected level to determine the state of the bus signal line.
摘要翻译：集成电路被配置为用于终止总线信号线的终止和非终止总线代理中的选定的一个。参考电平选择逻辑选择第一和第二不同的第二参考电平中的一个作为所选电平。集成电路将总线信号线与所选电平进行比较，以确定总线信号线的状态。

7. 发明授权

US06970011B2 Partial termination voltage current shunting 失效
公开(公告)号：US06970011B2
公开(公告)日：2005-11-29
申请号：US10724340
申请日：2003-11-28
申请人： Barry J. Arnold
发明人： Barry J. Arnold
IPC分类号： H03K19/003 , H04L25/08
CPC分类号： H04L25/0298
摘要： Termination circuitry is to terminate one or more lines and is to draw current from a termination voltage supply and through a termination voltage delivery network. Partial termination voltage current shunting may be used to help define a range of current variation through the termination voltage delivery network.

8. 发明申请

US20120005459A1 PROCESSOR HAVING INCREASED PERFORMANCE AND ENERGY SAVING VIA MOVE ELIMINATION 审中-公开
标题翻译：处理器具有增强的性能和通过移动消除的能量消耗
公开(公告)号：US20120005459A1
公开(公告)日：2012-01-05
申请号：US12979948
申请日：2010-12-28
申请人： Jay FLEISCHMAN , Matthew M. CRUM , Michael ESTLICK , Ranganathan SUDHAKAR , Emil TALPES , Ganesh VENKATARAMANAN , Barry J. Arnold , Michael Sedmak
发明人： Jay FLEISCHMAN , Matthew M. CRUM , Michael ESTLICK , Ranganathan SUDHAKAR , Emil TALPES , Ganesh VENKATARAMANAN , Barry J. Arnold , Michael Sedmak
IPC分类号： G06F9/30
CPC分类号： G06F9/384 , G06F9/30032 , G06F9/3017
摘要： Methods and apparatuses are provided for increasing processor performance and energy saving via eliminating physical data movement to accomplish a move instruction. The apparatus comprises a first plurality of available physical registers mapped to a second plurality of logical registers, including a source logical register and a destination logical register. A renaming unit remaps the destination logical register to the same physical register mapping as the source logical register in response to a move instruction. In this way, the move instruction is effectively executed without moving data between physical registers. A method is provided for increasing processor performance and energy saving via eliminating physical data movement to accomplish a move instruction. The method comprises determining a mapping of a logical source register and a logical destination register to physical registers of a processor and then remapping the logical destination register to the same physical register mapping as the logical source register to affect an equivalent of the move instruction with actual data movement between physical registers.
摘要翻译：提供了通过消除物理数据移动来实现移动指令来提高处理器性能和节能的方法和装置。该装置包括映射到包括源逻辑寄存器和目的地逻辑寄存器的第二多个逻辑寄存器的第一多个可用物理寄存器。重命名单元将目的地逻辑寄存器重新映射到与源逻辑寄存器相同的物理寄存器映射以响应移动指令。以这种方式，在不在物理寄存器之间移动数据的情况下，有效地执行移动指令。提供了一种通过消除物理数据移动来实现移动指令来提高处理器性能和节能的方法。该方法包括确定逻辑源寄存器和逻辑目标寄存器到处理器的物理寄存器的映射，然后将逻辑目标寄存器重映射到与逻辑源寄存器相同的物理寄存器映射，以影响具有实际值的移位指令的等效值物理寄存器之间的数据移动。

9. 发明授权

US07088130B2 Partial termination voltage current shunting 有权
标题翻译：部分端接电压分流
公开(公告)号：US07088130B2
公开(公告)日：2006-08-08
申请号：US11242402
申请日：2005-10-03
申请人： Barry J. Arnold
发明人： Barry J. Arnold
IPC分类号： H03K19/003
CPC分类号： H04L25/0298
摘要： An apparatus includes termination circuitry to terminate one or more lines. The termination circuitry draws a first current from a termination voltage supply through a termination voltage delivery network for each terminated line carrying a first signal. Partial current shunt circuitry draws a second current from the termination voltage supply through the termination voltage delivery network for each terminated line carrying a second signal. The first and second currents are distinct.
摘要翻译：一种装置包括用于终止一个或多个线路的终端电路。终端电路从终端电压源通过终端电压传送网络为承载第一信号的每个终止线路抽取第一电流。部分电流分路电路从终端电压源通过端接电压输送网络为承载第二信号的每个终端线路吸取第二电流。第一和第二电流是不同的。

10. 发明授权

US07202702B2 Output buffer slew rate control using clock signal 有权
标题翻译：输出缓冲器转换速率控制使用时钟信号
公开(公告)号：US07202702B2
公开(公告)日：2007-04-10
申请号：US10732687
申请日：2003-12-10
申请人： Barry J. Arnold , Kenneth Koch, II , Philip L. Barnes
发明人： Barry J. Arnold , Kenneth Koch, II , Philip L. Barnes
IPC分类号： H03K19/0175
CPC分类号： H03K19/00384
摘要： A signal generated by circuitry for an output buffer is identified relative to a clock signal to control a slew rate of the circuitry for an output buffer.
摘要翻译：由输出缓冲器的电路产生的信号相对于时钟信号被识别，以控制用于输出缓冲器的电路的转换速率。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式