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1. 发明授权

US08836443B2 Integrated circuits with configurable inductors 有权
标题翻译：具有可配置电感器的集成电路
公开(公告)号：US08836443B2
公开(公告)日：2014-09-16
申请号：US13617347
申请日：2012-09-14
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
IPC分类号： H01L23/66 , H03B5/08 , H03C3/22 , H01F27/29 , H03B5/12 , H01F27/28 , H01F21/12
CPC分类号： H03B5/1212 , H01F2021/125 , H01F2027/2809 , H01L2924/0002 , H03B5/1243 , H03B5/1268 , H01L2924/00
摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.
摘要翻译：提供具有锁相环的集成电路。锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。多个电感器中选择的一个可以主动地连接到振荡器电路。压控振荡器可以具有多个振荡器电路。每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

2. 发明授权

US08319564B2 Integrated circuits with configurable inductors 有权
标题翻译：具有可配置电感器的集成电路
公开(公告)号：US08319564B2
公开(公告)日：2012-11-27
申请号：US12748261
申请日：2010-03-26
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
IPC分类号： H03B5/12 , H03L1/00
CPC分类号： H03B5/1212 , H01F2021/125 , H01F2027/2809 , H01L2924/0002 , H03B5/1243 , H03B5/1268 , H01L2924/00
摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.
摘要翻译：提供具有锁相环的集成电路。锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。多个电感器中选择的一个可以主动地连接到振荡器电路。压控振荡器可以具有多个振荡器电路。每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

3. 发明申请

US20110234331A1 INTEGRATED CIRCUITS WITH CONFIGURABLE INDUCTORS 有权
标题翻译：集成电路与配置电感器
公开(公告)号：US20110234331A1
公开(公告)日：2011-09-29
申请号：US12748261
申请日：2010-03-26
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
IPC分类号： H03B5/12 , H01F5/00
CPC分类号： H03B5/1212 , H01F2021/125 , H01F2027/2809 , H01L2924/0002 , H03B5/1243 , H03B5/1268 , H01L2924/00
摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.
摘要翻译：提供具有锁相环的集成电路。锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。多个电感器中选择的一个可以主动地连接到振荡器电路。压控振荡器可以具有多个振荡器电路。每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

4. 发明授权

US08692582B1 Latched comparator circuitry 有权
标题翻译：锁存比较器电路
公开(公告)号：US08692582B1
公开(公告)日：2014-04-08
申请号：US13345384
申请日：2012-01-06
申请人： Ali Atesoglu , Weiqi Ding
发明人： Ali Atesoglu , Weiqi Ding
IPC分类号： H03K5/22
CPC分类号： H03K3/037 , H03K5/249
摘要： Integrated circuits having analog-to-digital converters are provided. Analog-to-digital converters may contain latched comparators. A latched comparator may include inputs configured to receive a differential input voltage signal, a differential reference voltage signal, and a clock signal. The comparator may include a preamplifier, a latching circuit, a level shifter, and a flip-flop coupled in series. The preamplifier may include large input transistors for minimizing offset, stacked tail transistors, and diode-connected load transistors for minimizing kickback noise. The preamplifier may be used to generate amplified voltage signals. The latching circuit may include a first pair of cross-coupled pull-down transistors, a second pair of cross-coupled pull-up transistors, and precharge transistors. The precharge transistors may serve to precharge the latch output to a predetermined voltage level during a first clock phase, whereas the first and second transistor pairs may serve to perform exponential regeneration on the amplified voltage signals during a second clock phase.
摘要翻译：提供了具有模数转换器的集成电路。模数转换器可能包含锁存的比较器。锁存的比较器可以包括被配置为接收差分输入电压信号，差分参考电压信号和时钟信号的输入。比较器可以包括前置放大器，锁存电路，电平移位器和串联耦合的触发器。前置放大器可以包括用于最小化偏移的堆叠尾部晶体管的大输入晶体管和用于最小化反冲噪声的二极管连接的负载晶体管。前置放大器可用于产生放大的电压信号。锁存电路可以包括第一对交叉耦合下拉晶体管，第二对交叉耦合上拉晶体管和预充电晶体管。预充电晶体管可以用于在第一时钟相位期间将锁存器输出预充电到预定电压电平，而第一和第二晶体管对可用于在第二时钟相位期间对放大的电压信号执行指数再生。

5. 发明申请

US20130009279A1 INTEGRATED CIRCUITS WITH CONFIGURABLE INDUCTORS 有权
标题翻译：集成电路与配置电感器
公开(公告)号：US20130009279A1
公开(公告)日：2013-01-10
申请号：US13617347
申请日：2012-09-14
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
IPC分类号： H01L27/08 , H01L21/20
CPC分类号： H03B5/1212 , H01F2021/125 , H01F2027/2809 , H01L2924/0002 , H03B5/1243 , H03B5/1268 , H01L2924/00
摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.
摘要翻译：提供具有锁相环的集成电路。锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。多个电感器中选择的一个可以主动地连接到振荡器电路。压控振荡器可以具有多个振荡器电路。每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

6. 发明授权

US09444656B2 Flexible receiver architecture 有权
标题翻译：灵活的接收机架构
公开(公告)号：US09444656B2
公开(公告)日：2016-09-13
申请号：US13289791
申请日：2011-11-04
申请人： Weiqi Ding , Sergey Shumarayev , Peng Li , Sriram Narayan
发明人： Weiqi Ding , Sergey Shumarayev , Peng Li , Sriram Narayan
IPC分类号： H04L25/03
CPC分类号： H04L25/03038 , H04L25/03146 , H04L2025/03573
摘要： One embodiment relates to a receiver circuit for a data link. The receiver circuit includes at least a first signal path, a second signal path, and a path selector circuit. The first signal path includes first equalization circuitry, and the second signal path includes second equalization circuitry. The path selector circuit is configured to select one signal path of the first and second signal paths. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及一种用于数据链路的接收机电路。接收机电路至少包括第一信号路径，第二信号路径和路径选择器电路。第一信号路径包括第一均衡电路，第二信号路径包括第二均衡电路。路径选择器电路被配置为选择第一和第二信号路径的一个信号路径。还公开了其它实施例和特征。

7. 发明授权

US08750406B2 Multi-level amplitude signaling receiver 有权
标题翻译：多电平振幅信号接收机
公开(公告)号：US08750406B2
公开(公告)日：2014-06-10
申请号：US13363098
申请日：2012-01-31
申请人： Mingde Pan , Weiqi Ding , Sergey Shumarayev , Peng Li , Masashi Shimanouchi
发明人： Mingde Pan , Weiqi Ding , Sergey Shumarayev , Peng Li , Masashi Shimanouchi
IPC分类号： H04L25/34 , H04L25/49
CPC分类号： H04L25/4917 , H03D1/00 , H04L25/066 , H04L27/06
摘要： One embodiment relates to a receiver circuit for multi-level amplitude signaling which includes at least three amplitude levels for each symbol period. The receiver circuit includes a peak detector, a reference voltage generator, and a comparator circuit. The peak detector is arranged to detect a peak voltage of the multi-level amplitude signal, and the reference voltage generator uses the peak voltage to generate multiple reference voltages. The comparator circuit uses the multiple reference voltages to detect an amplitude level of the multi-level amplitude signal. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及用于多电平振幅信令的接收机电路，其包括用于每个符号周期的至少三个幅度电平。接收器电路包括峰值检测器，参考电压发生器和比较器电路。峰值检测器被设置为检测多电平幅度信号的峰值电压，并且参考电压发生器使用峰值电压来产生多个参考电压。比较器电路使用多个参考电压来检测多电平幅度信号的幅度电平。还公开了其它实施例和特征。

8. 发明授权

US08610466B2 High-speed differential comparator circuitry with accurately adjustable threshold 有权
标题翻译：具有精确可调阈值的高速差分比较电路
公开(公告)号：US08610466B2
公开(公告)日：2013-12-17
申请号：US13540410
申请日：2012-07-02
申请人： Weiqi Ding , Mingde Pan
发明人： Weiqi Ding , Mingde Pan
IPC分类号： H03K5/22
CPC分类号： H03K3/356139 , H03K5/08
摘要： A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.
摘要翻译：高速差分比较器电路具有精确可调的阈值电压。提供差分参考电压信号来控制比较器的阈值电压。参考信号的共模电压优选地跟踪由比较器电路正在处理的差分高速串行数据信号的共模电压。

9. 发明授权

US08451883B1 On-chip full eye viewer architecture 有权
标题翻译：片上全景查看器架构
公开(公告)号：US08451883B1
公开(公告)日：2013-05-28
申请号：US12630674
申请日：2009-12-03
申请人： Weiqi Ding , Mingde Pan , Sergey Shumarayev , Peng Li
发明人： Weiqi Ding , Mingde Pan , Sergey Shumarayev , Peng Li
IPC分类号： H04B3/46
CPC分类号： G01R31/3171 , H04L1/0061 , H04L1/203 , H04L1/205 , H04L1/248 , H04L7/033 , H04L7/0334 , H04L7/048
摘要： Systems, methods, and devices for determining an eye diagram of a serial input signal to an integrated circuit without an oscilloscope are provided. For example, one embodiment of an integrated circuit device may be capable of determining an eye diagram associated with an equalized serial input signal. The device may include an equalizer and eye viewer circuitry. The equalizer may receive and perform equalization on a serial input signal to produce the equalized serial input signal, and the eye viewer circuitry may determine horizontal and vertical boundaries of the eye diagram associated with the equalized serial input signal.
摘要翻译：提供了用于确定没有示波器的集成电路的串行输入信号的眼图的系统，方法和装置。例如，集成电路设备的一个实施例可能能够确定与均衡的串行输入信号相关联的眼图。该装置可以包括均衡器和眼睛观察器电路。均衡器可以在串行输入信号上接收和执行均衡以产生均衡的串行输入信号，并且眼睛观察器电路可以确定与均衡的串行输入信号相关联的眼图的水平和垂直边界。

10. 发明授权

US08433958B2 Bit error rate checker receiving serial data signal from an eye viewer 有权
标题翻译：位错误率检测器从眼睛观察器接收串行数据信号
公开(公告)号：US08433958B2
公开(公告)日：2013-04-30
申请号：US12884923
申请日：2010-09-17
申请人： Weiqi Ding , Mingde Pan , Peng Li , Sergey Shumarayev , Masashi Shimanouchi
发明人： Weiqi Ding , Mingde Pan , Peng Li , Sergey Shumarayev , Masashi Shimanouchi
IPC分类号： G06F11/00
CPC分类号： H04L1/203 , G01R31/3171
摘要： An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.
摘要翻译：提供了一种IC，其包括耦合到眼睛观察者的眼睛观察器和BER检查器，其中BER检查器从眼睛观察器接收串行数据信号。在一个实现中，BER检查器从眼睛观察器接收串行数据信号，而不经过串行数据信号通过解串器。在一个实现中，BER检验器将串行数据信号与参考数据信号进行比较，以确定串行数据信号的BER。在一个实现中，IC包括耦合到眼睛观察器和BER检查器的IC核心，其中BER检验器在IC核心之外。在一个实现中，BER检查器是专用的BER检查器。在一个实现中，BER检查器包括异或门，耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。

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