专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4201603A Method of fabricating improved short channel MOS devices utilizing selective etching and counterdoping of polycrystalline silicon 失效
标题翻译：利用多晶硅的选择性蚀刻和反掺杂制造改进的短沟道MOS器件的方法
公开(公告)号：US4201603A
公开(公告)日：1980-05-06
申请号：US966510
申请日：1978-12-04
申请人： Joseph H. Scott, Jr. , Alfred C. Ipri
发明人： Joseph H. Scott, Jr. , Alfred C. Ipri
IPC分类号： H01L21/033 , H01L21/3213 , H01L21/3215 , H01L21/336 , H01L29/423 , H01L21/225 , H01L21/308
CPC分类号： H01L29/6678 , H01L21/033 , H01L21/32134 , H01L21/32155 , H01L29/42384 , Y10S148/106 , Y10S148/122 , Y10S148/15 , Y10S438/919 , Y10S438/967
摘要： A method for fabricating a short channel MOS device is described wherein the conductivity of the gate member is increased by a factor of about 2.5 by counterdoping a P-type doped polycrystalline line with an N-type dopant.
摘要翻译：描述了一种用于制造短沟道MOS器件的方法，其中通过用N型掺杂剂对P型掺杂多晶体线进行反掺杂，栅极部件的导电性增加约2.5倍。

2. 发明授权

US4169746A Method for making silicon on sapphire transistor utilizing predeposition of leads 失效
标题翻译：利用引线预沉积法在蓝宝石晶体管上制造硅的方法
公开(公告)号：US4169746A
公开(公告)日：1979-10-02
申请号：US930381
申请日：1978-08-02
申请人： Alfred C. Ipri , Joseph H. Scott, Jr.
发明人： Alfred C. Ipri , Joseph H. Scott, Jr.
IPC分类号： H01L21/205 , H01L21/3205 , H01L21/768 , H01L21/86 , H01L23/15 , H01L27/12 , H01L29/786 , H01L21/88 , H01L29/72
CPC分类号： H01L29/78657 , H01L21/32051 , H01L21/76885 , H01L21/86 , H01L23/15 , H01L27/12 , H01L29/78618 , H01L2924/0002 , Y10S148/147 , Y10S148/15
摘要： The integrated circuit is manufactured upside down relative to conventional silicon-on-sapphire (SOS) processing techniques for manufacturing field effect transistors. First a conductive pattern, typically of a refractory metal, is deposited and defined on an insulating substrate, such as sapphire, and then silicon transistors are formed over the conductive pattern. Using the process, a masking step, namely the contact definition mask, used in conventional SOS manufacture, is eliminated.
摘要翻译：相对于用于制造场效应晶体管的常规蓝宝石（SOS）处理技术，该集成电路被倒置制造。首先，通常是难熔金属的导电图案被沉积并限定在诸如蓝宝石的绝缘基板上，然后在导电图案上形成硅晶体管。使用该过程，消除了用于常规SOS制造中的掩蔽步骤，即接触定义掩模。

3. 发明授权

US4804640A Method of forming silicon and aluminum containing dielectric film and semiconductor device including said film 失效
标题翻译：形成含硅和铝的电介质膜的方法和包括所述膜的半导体器件
公开(公告)号：US4804640A
公开(公告)日：1989-02-14
申请号：US104451
申请日：1987-10-05
申请人： Grzegorz Kaganowicz , John W. Robinson , Alfred C. Ipri
发明人： Grzegorz Kaganowicz , John W. Robinson , Alfred C. Ipri
IPC分类号： C23C14/02 , C23C14/08 , H01L21/28 , H01L29/51 , H01L21/473
CPC分类号： H01L29/513 , C23C14/027 , C23C14/08 , C23C14/081 , H01L21/28273 , H01L29/517
摘要： A process of forming a three region dielectric film on silicon and a semiconductor device employing such a film are disclosed. Silicon is oxidized in an oxygen-containing ambient. The oxidation step forms a first region of silicon oxide. Once oxidation has begun, reactive sputtering of aluminum in an oxygen plasma is initiated. This forms a second region of said dielectric film which comprises a mixture of silicon and aluminum oxides. A third region comprising substantially aluminum oxide is formed by the continuing reactive sputtering step.A semiconductor device comprising said three region dielectric film interposed between an electrode and a semiconductor body has little or no shift in threshold voltage providing good stability and can be fabricated in substantially less time and/or at lower temperatures than prior art methods.
摘要翻译：公开了一种在硅上形成三区电介质膜的工艺和采用这种膜的半导体器件。硅在含氧环境中被氧化。氧化步骤形成氧化硅的第一区域。一旦氧化开始，则开始在氧等离子体中的铝的反应溅射。这形成了包括硅和氧化铝的混合物的所述电介质膜的第二区域。通过连续反应溅射步骤形成包含基本上氧化铝的第三区域。包括介于电极和半导体本体之间的所述三区电介质薄膜的半导体器件几乎没有或没有阈值电压的偏移提供良好的稳定性，并且可以在比现有技术方法更短的时间和/或更低的温度下制造。

4. 发明授权

US4791464A Semiconductor device that minimizes the leakage current associated with the parasitic edge transistors and a method of making the same 失效
标题翻译：使与寄生边缘晶体管相关联的漏电流最小化的半导体器件及其制造方法
公开(公告)号：US4791464A
公开(公告)日：1988-12-13
申请号：US048704
申请日：1987-05-12
申请人： Alfred C. Ipri , Dora Plus
发明人： Alfred C. Ipri , Dora Plus
IPC分类号： H01L27/12 , H01L29/786 , H01L29/78
CPC分类号： H01L27/12 , H01L29/78609
摘要： A semiconductor device comprising an island of semiconductor material disposed on an insulating substrate is disclosed. A MOS transistor is formed in the semiconductor island such that the gate electrode extends over the sidewalls of the island. Diodes are formed between the source and drain regions and the portions of the channel region along the sidewalls to electrically isolate the top transistor from the parasitic edge transistors.
摘要翻译：公开了一种包括设置在绝缘基板上的半导体材料岛的半导体器件。 MOS晶体管形成在半导体岛中，使得栅电极延伸在岛的侧壁上。在源极和漏极区域之间以及沿着侧壁的沟道区域的部分形成二极管以将顶部晶体管与寄生边缘晶体管电隔离。

5. 发明授权

US4530149A Method for fabricating a self-aligned vertical IGFET 失效
标题翻译：用于制造自对准垂直IGFET的方法
公开(公告)号：US4530149A
公开(公告)日：1985-07-23
申请号：US489307
申请日：1985-04-28
申请人： Lubomir L. Jastrzebski , Alfred C. Ipri , Achilles G. Kokkas
发明人： Lubomir L. Jastrzebski , Alfred C. Ipri , Achilles G. Kokkas
IPC分类号： H01L27/00 , H01L21/20 , H01L21/28 , H01L27/06 , H01L27/11 , H01L29/423 , H01L29/78 , H01L21/205
CPC分类号： H01L29/7827 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/28 , H01L27/0688 , H01L27/1104 , H01L29/66666 , H01L29/4236
摘要： A vertical IGFET device is formed on a substrate which includes a monocrystalline silicon portion at a surface thereof. An apertured insulated gate electrode is disposed on the substrate surface such that an area of monocrystalline silicon is exposed through the aperture. An epitaxial silicon region extends from the substrate surface within the gate electrode aperture and is appropriately doped such that a predetermined voltage applied to the insulated gate electrode forms a channel region in the epitaxial region adjacent thereto. The vertical IGFET is fabricated by a self-aligned technique, wherein the insulated gate electrode includes a first, underlying insulating layer and a second, overlying insulating layer. The second insulating layer protects the gate electrode when the first insulating layer is defined.
摘要翻译：在包括其表面的单晶硅部分的基板上形成垂直IGFET器件。多孔绝缘栅电极设置在衬底表面上，使得单晶硅的面积通过该孔露出。外延硅区域从栅电极孔内的衬底表面延伸并被适当地掺杂，使得施加到绝缘栅电极的预定电压在与其相邻的外延区域中形成沟道区。垂直IGFET通过自对准技术制造，其中绝缘栅电极包括第一下层绝缘层和第二覆盖绝缘层。当限定第一绝缘层时，第二绝缘层保护栅电极。

6. 发明授权

US4282556A Input protection device for insulated gate field effect transistor 失效
标题翻译：绝缘栅场效应晶体管的输入保护装置
公开(公告)号：US4282556A
公开(公告)日：1981-08-04
申请号：US41085
申请日：1979-05-21
申请人： Alfred C. Ipri
发明人： Alfred C. Ipri
IPC分类号： H01L27/02 , H01L29/423 , H03F1/52 , H03K17/0812 , H02H3/22
CPC分类号： H01L29/42384 , H01L27/0266 , H03F1/523 , H03K17/08122
摘要： An input protection device comprising at least one pair of N and P type MOSFETs having their conduction paths series connected between a source of operating potential and the input of the circuit to be protected. Another variation includes a second pair of similarly connected N and P type MOSFETs with one pair connected between the input to be protected and the most negative source of operating potential while the second pair is connected between the most positive source of operating potential and the input to be protected.
摘要翻译：一种输入保护装置，包括至少一对N型和P型MOSFET，它们的导通路径串联连接在工作电位源和待保护电路的输入端之间。另一种变化包括第二对类似连接的N型和P型MOSFET，其中一对连接在待保护的输入端和最负的工作电位之间，而第二对连接在最正的工作电源和输入端被保护。

7. 发明授权

US06417825B1 Analog active matrix emissive display 有权
标题翻译：模拟有源矩阵发射显示
公开(公告)号：US06417825B1
公开(公告)日：2002-07-09
申请号：US09200513
申请日：1998-11-25
申请人： Roger G. Stewart , Alfred C. Ipri
发明人： Roger G. Stewart , Alfred C. Ipri
IPC分类号： G09G330
CPC分类号： G09G3/30 , G09G3/2011 , G09G3/2018 , G09G3/2051 , G09G2300/0809 , G09G2300/0842
摘要： An emissive display device such as an active matrix electroluminescent display (AMEL display) has an improved method of operation. The AMEL display produces gray scale operation comprising an array of pixels, each pixel including a first transistor having its gate connected to a select line, its source connected to a data line, and its drain connected to the gate of a second transistor. The second transistor has its source adapted to receive a ramped voltage level, and its drain connected to a first electrode of an electroluminescent cell. The electroluminescent cell has a second electrode connected to an alternating current high voltage power source, wherein the electroluminescent cell is illuminated, when the ramp voltage level is less than a voltage level on the gate of the second transistor. The ramp voltage level is increased linearly during a frame duration, and the alternating current high voltage power source is on continuously during the same frame duration. The alternating current high voltage power source may also be varied in amplitude from a minimum peak-to-peak value to a maximum peak-to-peak value during the frame duration.
摘要翻译：诸如有源矩阵电致发光显示器（AMEL显示器）的发射显示装置具有改进的操作方法。 AMEL显示器产生包括像素阵列的灰度级操作，每个像素包括其栅极连接到选择线的第一晶体管，其源极连接到数据线，其漏极连接到第二晶体管的栅极。第二晶体管的源极适于接收斜坡电压电平，其漏极连接到电致发光单元的第一电极。电致发光单元具有连接到交流高压电源的第二电极，其中当斜坡电压电平小于第二晶体管的栅极上的电压电平时，电致发光单元被照亮。斜坡电压电平在帧持续时间内线性增加，并且交流电压高电压电源在相同的帧持续时间期间连续地连续。在帧持续时间期间，交流电压高压电源也可以从最小峰 - 峰值到最大峰 - 峰值的幅度变化。

8. 发明授权

US5076667A High speed signal and power supply bussing for liquid crystal displays 失效
标题翻译：液晶显示器的高速信号和电源总线
公开(公告)号：US5076667A
公开(公告)日：1991-12-31
申请号：US471566
申请日：1990-01-29
申请人： Roger G. Stewart , Alfred C. Ipri
发明人： Roger G. Stewart , Alfred C. Ipri
IPC分类号： G02F1/1345
CPC分类号： G02F1/1345
摘要： A Liquid Crystal Display device has first and second transparent substrates with a liquid crystal material sealed therebetween; a centrally disposed optically active display region having a matrix of pixels and a first and second scanner, and a transparent common electrode formed on the inner surface of the first and second transparent substrates, respectively; and a power supply and data signal distribution region surrounding at least a portion of the optically active display region and near the first and second scanners. The power supply and data signal distribution region comprises (a) a groove, and (b) a plurality of parallel conductors, formed on the inner surface of the second and first transparent substrates, respectively, which conductors include a height extending into the groove to reduce each conductor's resistance. Conductor capacitance is reduced by (a) eliminating the transparent common electrode from the groove, and/or (b) providing an inert dielectric material or gas in the distribution region with a lower dielectric constant than the liquid crystal material.
摘要翻译：液晶显示装置具有密封在其间的液晶材料的第一和第二透明基板; 分别具有像素矩阵和第一和第二扫描仪的中心布置的光学活性显示区域和分别形成在第一和第二透明基板的内表面上的透明公共电极; 以及围绕光学活动显示区域的至少一部分并且靠近第一和第二扫描器的电源和数据信号分配区域。电源和数据信号分配区域包括（a）分别形成在第二和第一透明基板的内表面上的凹槽和（b）多个平行导体，该导体包括延伸到凹槽中的高度减少每个导线的电阻。通过（a）从沟槽去除透明公共电极，和/或（b）在分布区域中提供比液晶材料低的介电常数的惰性电介质材料或气体来减小导体电容。

9. 发明授权

US4828365A Multicolor filter for producing purer white across a display device 失效
标题翻译：用于在显示设备上生产纯白色的多色滤光片
公开(公告)号：US4828365A
公开(公告)日：1989-05-09
申请号：US158954
申请日：1988-02-22
申请人： Roger G. Stewart , Alfred C. Ipri
发明人： Roger G. Stewart , Alfred C. Ipri
IPC分类号： G02B5/20 , G02F1/1335 , G02F1/13357
CPC分类号： G02F1/133514 , G02F2201/52
摘要： A multicolor filter for a display device includes separate filter elements for individually providing the primary colors of light. The areas of the filter elements are tailored in accordance with the percentages of primary light colors in pure white light, the percentages of primary light in the illuminating source, and the light transmission capabilities of the filter elements. Additionally, the filter elements are configured so that the centroid of the filter elements are within the close proximity of a straight line passing through adjacent filter elements.

10. 发明授权

US4566025A CMOS Structure incorporating vertical IGFETS 失效
标题翻译： CMOS结构采用垂直IGFETS
公开(公告)号：US4566025A
公开(公告)日：1986-01-21
申请号：US503044
申请日：1983-06-10
申请人： Lubomir L. Jastrzebski , Alfred C. Ipri
发明人： Lubomir L. Jastrzebski , Alfred C. Ipri
IPC分类号： H01L27/00 , H01L21/20 , H01L21/28 , H01L27/06 , H01L27/11 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7827 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/28 , H01L27/0688 , H01L27/1104 , H01L29/66666 , H01L29/4236
摘要： A CMOS device incorporates a plurality of interconnected vertical IGFETs on a substrate. An insulated gate electrode is located on the substrate surface and a pair of monocrystalline silicon regions extend from the substrate surface such that each of the monocrystalline silicon regions is contiguous with a portion of the insulated gate electrode. One of the monocrystalline regions has a body region of first conductivity type and the other monocrystalline region has a body region of second conductivity type. Both of the body regions are located with respect to the insulated gate electrode such that an inversion channel can selectively be created in one of the body regions by applying a predetermined voltage to the insulated gate electrode.
摘要翻译： CMOS器件在衬底上并入多个互连的垂直IGFET。绝缘栅电极位于衬底表面上，并且一对单晶硅区域从衬底表面延伸，使得每个单晶硅区域与绝缘栅电极的一部分相邻。单晶区域之一具有第一导电类型的体区，而另一单晶区具有第二导电类型的体区。两个主体区域相对于绝缘栅电极定位，使得可以通过向绝缘栅电极施加预定电压来选择性地在一个身体区域中产生反转通道。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式