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1. 发明授权

US06918007B2 Memory controller interface with XOR operations on memory read to accelerate RAID operations 有权
标题翻译：内存控制器接口通过XOR操作对存储器进行读取，以加速RAID操作
公开(公告)号：US06918007B2
公开(公告)日：2005-07-12
申请号：US10237330
申请日：2002-09-09
申请人： Albert H. Chang , Jeff M. Carlson , Christopher Garza , Mark J. Thompson
发明人： Albert H. Chang , Jeff M. Carlson , Christopher Garza , Mark J. Thompson
IPC分类号： G06F11/10 , G06F12/00
CPC分类号： G06F11/1076 , G06F2211/1054
摘要： A single read request to a memory controller generates multiple read actions along with XOR/DATUM manipulation of that read data. Fewer memory transfers are required to accomplish a RAID5/DATUM parity update. This allows for higher system performance when memory bandwidth is the limiting system component. In implementation, a read buffer with XOR capability is tightly coupled to a memory controller. New parity does not need to be stored in the controller's memory. Instead, a memory read initiates multiple reads from memory based on an address decode. The data from the reads are multiplied and XOR'd before being returned to the requestor. In the case of a PCI-X requestor, this occurs as a split-completion.
摘要翻译：对存储器控制器的单个读取请求产生多个读取操作以及该读取数据的XOR / DATUM操作。需要更少的内存传输来完成RAID 5 / DATUM奇偶校验更新。当存储器带宽是限制系统组件时，这允许更高的系统性能。在实现中，具有XOR能力的读缓冲器与存储器控制器紧密耦合。新奇偶校验不需要存储在控制器的存储器中。相反，存储器读取基于地址解码来从存储器发起多次读取。读取的数据在被返回给请求者之前被乘以XOR'd。在PCI-X请求者的情况下，这是分裂完成。

2. 发明授权

US06754780B1 Providing data in response to a read command that maintains cache line alignment 失效
标题翻译：提供数据以响应维护高速缓存行对齐的读取命令
公开(公告)号：US06754780B1
公开(公告)日：2004-06-22
申请号：US09542969
申请日：2000-04-04
申请人： Jeff M. Carlson , Ryan A. Callison
发明人： Jeff M. Carlson , Ryan A. Callison
IPC分类号： G06F1200
CPC分类号： G06F12/0877 , G06F12/04 , G06F12/0862
摘要： Efficient memory operation is provided by maintaining alignment with cache line boundaries in response to a read command. A prefetching scheme is used to limit the amount of operations needed to respond to a read command. In addition, the prefetch amount is initially adjusted where the starting address of the read request falls in between cache line boundaries. The adjusted read amount is determined based on the misaligned portion from the starting address of the read request to the nearest cache line boundary outside of the requested data block, such that the adjusted read amount ends on a cache line boundary. Subsequent read requests to the same data block will thereby begin at the last cache line boundary and end upon a subsequent cache line boundary by providing the pre-configured prefetch data amount corresponding to the requesting master device. Efficient bus utilization and memory controller operation efficiency is maximized by allowing the memory control to operate and respond to read requests in data amounts maintaining cache line alignment.
摘要翻译：响应于读取命令，通过保持与高速缓存线边界的对准来提供高效的存储器操作。预取方案用于限制响应读取命令所需的操作量。另外，在读取请求的起始地址落在高速缓存行边界之间的情况下，最初调整预取量。基于从读取请求的开始地址到所请求的数据块之外的最近的高速缓存行边界的未对准部分确定调整后的读取量，使得调整的读取量在高速缓存行边界上结束。因此，对相同数据块的后续读取请求将在最后的高速缓存行边界开始，并通过提供与请求主设备相对应的预先配置的预取数据量而在随后的高速缓存行边界上结束。通过允许存储器控制来操作和响应以维持高速缓存线对齐的数据量的读请求来最大化总线利用率和存储器控制器操作效率。

3. 发明申请

US20140164471A1 APPARATUS AND METHOD FOR IN-LINE INSERTION AND REMOVAL OF MARKERS 有权
标题翻译：用于在线插入和删除标记的装置和方法
公开(公告)号：US20140164471A1
公开(公告)日：2014-06-12
申请号：US14183133
申请日：2014-02-18
申请人： Kenneth G. Keels , Jeff M. Carlson , Brian S. Hausauer , David J. Maguire
发明人： Kenneth G. Keels , Jeff M. Carlson , Brian S. Hausauer , David J. Maguire
IPC分类号： H04L29/08
CPC分类号： H04L67/02 , H04L49/90 , H04L49/9094 , H04L69/12
摘要： An apparatus is provided, for performing a direct memory access (DMA) operation between a host memory in a first server and a network adapter. The apparatus includes a host frame parser and a protocol engine. The host frame parser is configured to receive data corresponding to the DMA operation from a host interface, and is configured to insert markers on-the-fly into the data at a prescribed interval and to provide marked data for transmission to a second server over a network fabric. The protocol engine is coupled to the host frame parser. The protocol engine is configured to direct the host frame parser to insert the markers, and is configured to specify a first marker value and an offset value, whereby the host frame parser is enabled to locate and insert a first marker into the data.
摘要翻译：提供了一种用于在第一服务器中的主机存储器和网络适配器之间执行直接存储器访问（DMA）操作的装置。该装置包括主机帧解析器和协议引擎。主机帧解析器被配置为从主机接口接收对应于DMA操作的数据，并且被配置为以规定的间隔将动态的标记插入到数据中，并提供标记的数据，以便通过一个网络结构。协议引擎耦合到主机帧解析器。协议引擎被配置为指导主机帧解析器插入标记，并且被配置为指定第一标记值和偏移值，由此使主机帧解析器能够定位并将第一标记插入到数据中。

4. 发明授权

US08699521B2 Apparatus and method for in-line insertion and removal of markers 有权
标题翻译：用于在线插入和移除标记物的装置和方法
公开(公告)号：US08699521B2
公开(公告)日：2014-04-15
申请号：US12986665
申请日：2011-01-07
申请人： Kenneth G. Keels , Jeff M. Carlson , Brian S. Hausauer , David J. Maguire
发明人： Kenneth G. Keels , Jeff M. Carlson , Brian S. Hausauer , David J. Maguire
IPC分类号： H04L1/00
CPC分类号： H04L67/02 , H04L49/90 , H04L49/9094 , H04L69/12
摘要： An apparatus is provided, for performing a direct memory access (DMA) operation between a host memory in a first server and a network adapter. The apparatus includes a host frame parser and a protocol engine. The host frame parser is configured to receive data corresponding to the DMA operation from a host interface, and is configured to insert markers on-the-fly into the data at a prescribed interval and to provide marked data for transmission to a second server over a network fabric. The protocol engine is coupled to the host frame parser. The protocol engine is configured to direct the host frame parser to insert the markers, and is configured to specify a first marker value and an offset value, whereby the host frame parser is enabled to locate and insert a first marker into the data.
摘要翻译：提供了一种用于在第一服务器中的主机存储器和网络适配器之间执行直接存储器访问（DMA）操作的装置。该装置包括主机帧解析器和协议引擎。主机帧解析器被配置为从主机接口接收对应于DMA操作的数据，并且被配置为以规定的间隔将动态的标记插入到数据中，并提供标记的数据，以便通过一个网络结构。协议引擎耦合到主机帧解析器。协议引擎被配置为指导主机帧解析器插入标记，并且被配置为指定第一标记值和偏移值，由此使主机帧解析器能够定位并将第一标记插入到数据中。

5. 发明申请

US20110099243A1 APPARATUS AND METHOD FOR IN-LINE INSERTION AND REMOVAL OF MARKERS 有权
标题翻译：用于在线插入和删除标记的装置和方法
公开(公告)号：US20110099243A1
公开(公告)日：2011-04-28
申请号：US12986665
申请日：2011-01-07
申请人： Kenneth G. Keels , Jeff M. Carlson , Brian S. Hausauer , David J. Maguire
发明人： Kenneth G. Keels , Jeff M. Carlson , Brian S. Hausauer , David J. Maguire
IPC分类号： G06F15/167
CPC分类号： H04L67/02 , H04L49/90 , H04L49/9094 , H04L69/12
摘要： An apparatus is provided, for performing a direct memory access (DMA) operation between a host memory in a first server and a network adapter. The apparatus includes a host frame parser and a protocol engine. The host frame parser is configured to receive data corresponding to the DMA operation from a host interface, and is configured to insert markers on-the-fly into the data at a prescribed interval and to provide marked data for transmission to a second server over a network fabric. The protocol engine is coupled to the host frame parser. The protocol engine is configured to direct the host frame parser to insert the markers, and is configured to specify a first marker value and an offset value, whereby the host frame parser is enabled to locate and insert a first marker into the data.
摘要翻译：提供了一种用于在第一服务器中的主机存储器和网络适配器之间执行直接存储器访问（DMA）操作的装置。该装置包括主机帧解析器和协议引擎。主机帧解析器被配置为从主机接口接收对应于DMA操作的数据，并且被配置为以规定的间隔将动态的标记插入到数据中，并提供标记的数据，以便通过一个网络结构。协议引擎耦合到主机帧解析器。协议引擎被配置为指导主机帧解析器插入标记，并且被配置为指定第一标记值和偏移值，由此使主机帧解析器能够定位并将第一标记插入到数据中。

6. 发明授权

US06807590B1 Disconnecting a device on a cache line boundary in response to a write command 失效
标题翻译：响应于写命令，断开缓存线边界上的设备
公开(公告)号：US06807590B1
公开(公告)日：2004-10-19
申请号：US09542157
申请日：2000-04-04
申请人： Jeff M. Carlson , Ryan A. Callison
发明人： Jeff M. Carlson , Ryan A. Callison
IPC分类号： G06F1314
CPC分类号： G06F12/0802 , G06F2212/306
摘要： Efficient bus operations is provided by maintaining alignment with cache line boundaries in response to a write command. A write buffer in a bridge device receives data from any one of a multiple number of bus interfaces. Write buffer management is utilized to monitor on a continuous basis the amount of free space available in the write buffer. When the data in the write buffer approaches the capacity of the write buffer, the system prepares for a potential disconnect of the write initiating device from the bridge device. Data alignment with cache line boundaries is maintained upon disconnect by adjusting the available free space in the write buffer to equal a multiple of a cache line amount of data. The write initiating device is disconnected when the data in the write buffer equals a write buffer full status.
摘要翻译：响应于写命令，通过保持与高速缓存线边界的对准来提供有效的总线操作。桥接器件中的写入缓冲器从多个总线接口中的任何一个接收数据。写缓冲区管理用于连续监视写入缓冲区中可用空间的数量。当写缓冲区中的数据接近写入缓冲器的容量时，系统准备写入启动设备与桥接器件的潜在断开。通过调整写入缓冲器中的可用空闲空间等于高速缓存行数据量的倍数来保持与高速缓存线边界的数据对齐。当写入缓冲区中的数据等于写入缓冲区满状态时，写入启动设备被断开。

7. 发明授权

US5717954A Locked exchange FIFO 失效
标题翻译：锁定交换FIFO
公开(公告)号：US5717954A
公开(公告)日：1998-02-10
申请号：US542801
申请日：1995-10-13
申请人： Thomas W. Grieff , William C. Galloway , Jeff M. Carlson
发明人： Thomas W. Grieff , William C. Galloway , Jeff M. Carlson
IPC分类号： G06F5/06 , G06F5/10 , G06F5/12 , G06F5/14
CPC分类号： G06F5/14 , G06F5/06 , G06F5/12 , G06F2205/123
摘要： A FIFO with locked exchange capability is disclosed. The FIFO has a memory for storing and retrieving data submissions, a write address generator and a read address generator for sequentially addressing the memory. A difference counter maintains the difference between the number of writes to the queue and reads from the queue. The net difference, as tracked by the counter is a measure of the FIFO utilization. To detect the queue full condition, a comparator compares the maximum FIFO stack depth against the counter output. The result of this comparison is latched and provided to a write strobe generator so that, in a subsequent write operation, if the FIFO is full, the write strobe from the producer is blocked and the data will not be written to the FIFO. Otherwise, the write strobe from the producer is passed to the memory. Additionally, a remaining space count is maintained in a status register. During operation, a bus master performing the read-modify-write cycle to the FIFO reads the status register to find the available space in the FIFO and immediately writes the data to the FIFO. If the read returns a zero, indicating that the FIFO is full, the bus master requeues the data for another read- modify-write cycle as it knows that the data has not been stored in the FIFO.
摘要翻译：公开了具有锁定交换能力的FIFO。 FIFO具有用于存储和检索数据提交的存储器，用于顺序寻址存储器的写地址生成器和读地址生成器。差异计数器维护对队列的写入次数和从队列读取的差异。由计数器跟踪的净差是FIFO利用率的度量。为了检测队列满状态，比较器比较最大FIFO堆栈深度与计数器输出。该比较的结果被锁存并提供给写选通发生器，使得在随后的写操作中，如果FIFO已满，则来自制造者的写选通信号被阻塞，并且数据将不被写入FIFO。否则，来自生产者的写选通传递到存储器。此外，在状态寄存器中保留剩余空间数。在操作期间，执行FIFO读读修改周期的总线主机读取状态寄存器以找到FIFO中的可用空间，并立即将数据写入FIFO。如果读取返回零，表示FIFO已满，则总线主机将数据重新读取以进行另一个读 - 修改 - 写入周期，因为它知道数据尚未存储在FIFO中。

8. 发明授权

US07889762B2 Apparatus and method for in-line insertion and removal of markers 有权
标题翻译：用于在线插入和移除标记物的装置和方法
公开(公告)号：US07889762B2
公开(公告)日：2011-02-15
申请号：US11624849
申请日：2007-01-19
申请人： Kenneth G. Keels , Jeff M. Carlson , Brian S. Hausauer , David J. Maguire
发明人： Kenneth G. Keels , Jeff M. Carlson , Brian S. Hausauer , David J. Maguire
IPC分类号： H04J3/24
CPC分类号： H04L67/02 , H04L49/90 , H04L49/9094 , H04L69/12
摘要： An apparatus is provided, for performing a direct memory access (DMA) operation between a host memory in a first server and a network adapter. The apparatus includes a host frame parser and a protocol engine. The host frame parser is configured to receive data corresponding to the DMA operation from a host interface, and is configured to insert markers on-the-fly into the data at a prescribed interval and to provide marked data for transmission to a second server over a network fabric. The protocol engine is coupled to the host frame parser. The protocol engine is configured to direct the host frame parser to insert the markers, and is configured to specify a first marker value and an offset value, whereby the host frame parser is enabled to locate and insert a first marker into the data.
摘要翻译：提供了一种用于在第一服务器中的主机存储器和网络适配器之间执行直接存储器访问（DMA）操作的装置。该装置包括主机帧解析器和协议引擎。主机帧解析器被配置为从主机接口接收对应于DMA操作的数据，并且被配置为以规定的间隔将动态的标记插入到数据中，并提供标记的数据，以便通过一个网络结构。协议引擎耦合到主机帧解析器。协议引擎被配置为指导主机帧解析器插入标记，并且被配置为指定第一标记值和偏移值，由此使主机帧解析器能够定位并将第一标记插入到数据中。

9. 发明授权

US5692200A Bridge circuit for preventing data incoherency by holding off propagation of data transfer completion interrupts until data clears the bridge circuit 失效
标题翻译：桥接电路，用于通过阻止数据传输完成中断的传播来防止数据不连贯，直到数据清除桥接电路
公开(公告)号：US5692200A
公开(公告)日：1997-11-25
申请号：US543724
申请日：1995-10-16
申请人： Jeff M. Carlson , William C. Galloway
发明人： Jeff M. Carlson , William C. Galloway
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4059
摘要： A bridge circuit for holding off primary interrupts signaling the completion of a block data transfer from a second bus to a system bus until the data has cleared the bridge circuit. The bridge circuit includes an interrupt control circuit for receiving up to seven primary interrupt signals corresponding to seven sets of bus grant-request lines on a second bus. Each bus grant-request set is assigned a data FIFO for synchronizing the transfer of data from the second bus to a system bus. The interrupt control circuit provides an interrupt to the system bus which corresponds to the primary interrupt only after the associated data FIFO is empty, thereby preventing data coherency problems in system memory.
摘要翻译：用于阻止主中断的桥接电路，用于向数据清除桥接电路指示完成从第二总线到系统总线的块数据传输。桥接电路包括一个中断控制电路，用于在第二总线上接收与七组总线授权请求线对应的多达七个主中断信号。为每个总线授权请求集分配一个数据FIFO，用于使从第二总线到系统总线的数据传输同步。中断控制电路只有在相关的数据FIFO为空之后，才能对与主中断相对应的系统总线提供中断，从而防止系统内存中的数据一致性问题。

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