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1. 发明授权

US06700177B2 Compact, surface-mounting-type, electronic-circuit unit 失效
标题翻译：紧凑型表面安装型电子电路单元
公开(公告)号：US06700177B2
公开(公告)日：2004-03-02
申请号：US09867919
申请日：2001-05-29
申请人： Akiyuki Yoshisato , Kazuhiko Ueda , Hiroshi Sakuma , Akihiko Inoue
发明人： Akiyuki Yoshisato , Kazuhiko Ueda , Hiroshi Sakuma , Akihiko Inoue
IPC分类号： H01L2166
CPC分类号： H05K3/403 , H01L23/66 , H01L24/48 , H01L27/016 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15313 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0306 , H05K1/092 , H05K1/16 , H05K3/246 , H05K2201/0317 , H05K2201/0347 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： In a surface-mounting-type electronic-circuit unit, circuit elements, including capacitors, resistors, and inductive devices, and electrically conductive patterns connected to the circuit elements are formed on an alumina board as thin films. Semiconductor bare chips for a diode and a transistor are wire-bonded to connection lands in electrically conductive patterns. And end-face electrodes connected to grounding electrodes, input electrodes, and output electrodes of electrically conductive patterns are formed at side faces of the alumina board.
摘要翻译：在表面安装型电子电路单元中，包括电容器，电阻器和电感器件的电路元件以及连接到电路元件的导电图案在氧化铝板上形成为薄膜。用于二极管和晶体管的半导体裸芯片以导电图案引线接合到连接焊盘。在氧化铝板的侧面形成有与导电图案的接地电极，输入电极和输出电极连接的端面电极。

2. 发明授权

US06714420B2 Electronic circuit unit that is suitable for miniaturization and suitable for simple output adjustment 失效
标题翻译：适用于小型化，适合简单输出调整的电子电路单元
公开(公告)号：US06714420B2
公开(公告)日：2004-03-30
申请号：US09870415
申请日：2001-05-29
申请人： Akiyuki Yoshisato , Kazuhiko Ueda , Yasuhiro Ikarashi , Akihiko Inoue , Hiroshi Sakuma
发明人： Akiyuki Yoshisato , Kazuhiko Ueda , Yasuhiro Ikarashi , Akihiko Inoue , Hiroshi Sakuma
IPC分类号： H05K116
CPC分类号： H05K3/403 , H01L23/647 , H01L24/48 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15313 , H01L2924/181 , H01L2924/19015 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0306 , H05K1/092 , H05K1/16 , H05K3/246 , H05K2201/0317 , H05K2201/0347 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2924/00
摘要： The invention provides a surface mounting type electronic circuit unit that is suitable for miniaturization and is suitable for simple output adjustment. Circuit elements including capacitors, resistors, and inductance elements and a conducting pattern connected to the circuit elements are formed on an alumina substrate by means of thin film forming technique, and a diode D1 and a semiconductor chip of a transistor are fixed to a connection land of the conducting pattern by means of wire bonding, wherein only the emitter resistor out of the base bias voltage dividing resistors and the emitter resistor of the transistor is trimmed for output adjustment.
摘要翻译：本发明提供一种适合小型化的表面安装型电子电路单元，适用于简单的输出调整。通过薄膜形成技术在氧化铝基板上形成包括电容器，电阻器和电感元件的电路元件和连接到电路元件的导电图案，并且将二极管D1和晶体管的半导体芯片固定到连接区域的导线图案，其中仅偏压基极偏压分压电阻器中的发射极电阻器和晶体管的发射极电阻器被修整以用于输出调节。

3. 发明授权

US06603667B2 Electronic circuit unit that is suitable for miniaturization and excellent in high frequency characteristic 失效
公开(公告)号：US06603667B2
公开(公告)日：2003-08-05
申请号：US09870416
申请日：2001-05-29
申请人： Akiyuki Yoshisato , Kazuhiko Ueda , Akihiko Inoue , Hiroshi Sakuma
发明人： Akiyuki Yoshisato , Kazuhiko Ueda , Akihiko Inoue , Hiroshi Sakuma
IPC分类号： H05K706
CPC分类号： H05K3/403 , H01L23/66 , H01L24/48 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15313 , H01L2924/19041 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0306 , H05K1/092 , H05K3/246 , H05K2201/0317 , H05K2201/0347 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2224/45099
摘要： The invention provides an electronic circuit unit that is suitable for miniaturization and excellent in high frequency characteristic. Capacitors and a wiring pattern are formed on an alumina substrate by means of thin film forming technique, and a part of the wiring pattern is served as the connection land for mounting a bare chip of a transistor. Among the capacitors, the top electrode of the capacitor is served also as a part of the connection land, and the bottom side collector electrode of the bare chip is connected to the connection land by use of conductive adhesive. Top electrodes of the residual capacitors are served as the bonding pad, and the base electrode and the emitter electrode on the top side of the bare chip are connected to the top electrodes of the respective capacitors by a wire.

4. 发明授权

US06518658B2 Surface-mounting type electronic circuit unit suitable for miniaturization 失效
公开(公告)号：US06518658B2
公开(公告)日：2003-02-11
申请号：US09870384
申请日：2001-05-29
申请人： Akiyuki Yoshisato , Kazuhiko Ueda , Yasuhio Ikarashi , Akihiko Inoue , Hiroshi Sakuma
发明人： Akiyuki Yoshisato , Kazuhiko Ueda , Yasuhio Ikarashi , Akihiko Inoue , Hiroshi Sakuma
IPC分类号： H01L2312
CPC分类号： H02M7/003 , H01L23/66 , H01L24/48 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15313 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/16 , H05K3/403 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： To provide a surface-mounting type electronic circuit unit suitable for miniaturization, circuit elements including capacitors, resistors and inductance elements and a conductive pattern connected to these circuit elements are thinly formed on an alumina substrate, semiconductor bare chips for a diode and a transistor are bonded on a connection land of the conductive pattern via wire, an inductance element composed of a pair of conductors opposite at a predetermined interval on the aluminum board is thinly formed and a unbalance/balance converter is formed by these conductors.

5. 发明授权

US07119443B2 Semiconductor integrated circuit device having a conductive film which contains metal atoms bondable to a halogen element 有权
标题翻译：具有导电膜的半导体集成电路器件，其包含可与卤素元件键合的金属原子
公开(公告)号：US07119443B2
公开(公告)日：2006-10-10
申请号：US10959634
申请日：2004-10-07
申请人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
发明人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/31 , H01L21/469
CPC分类号： H01L27/10852 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.
摘要翻译：根据以下步骤形成半导体器件。通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀仅留下通孔66的内部并形成插头73。然后，通过溅射法将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，然后，将Ti膜76，Al合金膜75，并且将TiN膜74图案化以形成第二层布线77和78。

6. 发明授权

US06853081B2 Method for fabricating semiconductor integrated circuit 有权
标题翻译：制造半导体集成电路的方法
公开(公告)号：US06853081B2
公开(公告)日：2005-02-08
申请号：US10453611
申请日：2003-06-04
申请人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
发明人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
IPC分类号： H01L21/8242 , H01L23/522 , H01L23/48 , H01L21/44 , H01L21/4763 , H01L23/52 , H01L29/40
CPC分类号： H01L27/10852 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.
摘要翻译：根据以下步骤形成半导体器件。通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀仅留下通孔66的内部并形成插头73.然后，将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，通过溅射法，然后对Ti膜76，Al合金膜75和TiN膜74进行图案化以形成第二层布线77和78。

7. 发明授权

US06605530B2 Method for fabricating semiconductor integrated circuit 有权
公开(公告)号：US06605530B2
公开(公告)日：2003-08-12
申请号：US10287616
申请日：2002-11-05
申请人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
发明人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
IPC分类号： H01L214763
CPC分类号： H01L27/10852 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

8. 发明授权

US07845231B2 Shear measuring method and its device 有权
标题翻译：剪切测量方法及其装置
公开(公告)号：US07845231B2
公开(公告)日：2010-12-07
申请号：US12088046
申请日：2006-09-27
申请人： Kazue Kurihara , Hiroshi Sakuma , Masashi Mizukami
发明人： Kazue Kurihara , Hiroshi Sakuma , Masashi Mizukami
IPC分类号： G01H13/00 , G01N3/24
CPC分类号： G01N19/04 , G01N2203/0025
摘要： A resonance shear measuring method capable of simple and rapid measurement by obtaining a resonance shear curve through Fourier transformation of a damping curve of an oscillation on one side surface of a sample during measurement of shear response from the sample is provided. The method is to measure shear response of the sample sandwiched between the solid surfaces of a resonance shear measurement unit along with a change in film thickness by applying an input signal Uin to a horizontal driving section of the shear resonance measurement unit, by detecting an oscillation on one side surface of the sample sandwiched between solid surfaces of the resonance shear measurement unit as an output signal Uout by means of a displacement gauge, and by applying the output signal Uout along with the input signal Uin to a resonance shear signal analyzer, wherein a damping curve of the oscillation on one side surface of the sample is Fourier transformed by a Fourier transformation section (5B) to obtain a resonance shear curve. Also provided is a twin-path type apparatus for shear stress measurement capable of precise measurement of shear stress by using a twin-path method by which a distance between opaque substrates can be measured.
摘要翻译：提供一种共振剪切测量方法，其能够通过在从样品的剪切响应测量期间在样品的一个侧表面上的振荡的阻尼曲线通过傅里叶变换获得共振剪切曲线来简单且快速地测量。该方法是通过将输入信号Uin施加到剪切共振测量单元的水平驱动部分，通过检测振荡来测量夹在共振剪切测量单元的固体表面之间的样品的剪切响应以及膜厚度的变化在夹持在谐振剪切测量单元的固体表面之间的样品的一个侧表面上，通过位移计将输出信号Uout与输入信号Uin一起施加到谐振剪切信号分析仪，其中，通过傅立叶变换部（5B）对样品的一个侧面的振动的阻尼曲线进行傅里叶变换，得到共振剪切曲线。还提供了一种用于剪切应力测量的双路型装置，其能够通过使用可以测量不透明基板之间的距离的双路径方法来精确测量剪切应力。

9. 发明授权

US07256144B2 Method for forming a metal oxide film 有权
标题翻译：金属氧化物膜的形成方法
公开(公告)号：US07256144B2
公开(公告)日：2007-08-14
申请号：US10808193
申请日：2004-03-24
申请人： Kenichi Koyanagi , Hiroshi Sakuma
发明人： Kenichi Koyanagi , Hiroshi Sakuma
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02271 , C23C16/405 , C23C16/45525 , H01L21/02175 , H01L21/02181 , H01L21/02183 , H01L21/02186 , H01L21/3141 , H01L21/31637 , H01L27/10852 , H01L28/84 , H01L28/90
摘要： A method for forming a capacitor insulation film includes the step of depositing a monoatomic film made of a metal by supplying a metal source including the metal and no oxygen, and depositing a metal oxide film including the metal by using a CVD technique. The method provides the metal oxide film having higher film properties with a higher throughput.
摘要翻译：一种形成电容器绝缘膜的方法包括通过提供包括金属和不含氧的金属源沉积由金属制成的单原子膜并通过CVD技术沉积包括金属的金属氧化物膜的步骤。该方法提供具有较高膜特性并具有较高生产量的金属氧化物膜。

10. 发明授权

US07074669B2 Semiconductor integrated circuit device with capacitor of crown structure and method of manufacturing the same 失效
公开(公告)号：US07074669B2
公开(公告)日：2006-07-11
申请号：US10443572
申请日：2003-05-22
申请人： Shinpei Iijima , Hiroshi Sakuma
发明人： Shinpei Iijima , Hiroshi Sakuma
IPC分类号： H01L21/8242
CPC分类号： H01L28/65 , H01L21/31604 , H01L27/10814 , H01L27/10855 , H01L27/10882 , H01L27/10894 , H01L28/75 , H01L28/90
摘要： A semiconductor integrated circuit device includes a plurality of capacitor elements, which are separated from each other by a first insulating film on a plane. Each of the plurality of capacitor elements has a lower electrode, a dielectric film, and an upper electrode, and the lower electrode has a crown structure. At least one of the lower electrode and the upper electrode has a laminate structure composed of a plurality of conductive films. An outermost film of the laminate structure on a side of the dielectric film is a ruthenium film, and a portion of the laminate structure other than the outermost film has higher selective growth than the first insulating film with respect to the ruthenium film. Here, the first insulating film is desirably a tantalum oxide film.

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