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1. 发明授权

US5483175A Method for circuits connection for wafer level burning and testing of individual dies on semiconductor wafer 失效
标题翻译：半导体晶片上晶圆级燃烧和单个晶片测试电路连接方法
公开(公告)号：US5483175A
公开(公告)日：1996-01-09
申请号：US209665
申请日：1994-03-09
申请人： Aftab Ahmad , Larren G. Weber , Robert S. Green
发明人： Aftab Ahmad , Larren G. Weber , Robert S. Green
IPC分类号： G01R31/30 , G06F11/27 , G01R31/28 , H01L21/66
CPC分类号： G01R31/30 , G06F11/27
摘要： Integrated circuit devices on a wafer are tested by the use of test circuit on the integrated circuit devices which is connected by means of a grid. The grid is used to enable the test circuitry, and provides an ability to test the devices while still on the wafer. This facilitates burning in the wafer prior to singulating the parts, since it is not necessary to separately establish electrical connections at contact points on the individual integrated circuit devices. In one embodiment, an oscillator may be adjusted in speed so that further tests may be effected by changing a test speed through the test circuit. Response of the integrated circuits at different operating speeds is determined by the adjustment of the oscillator speed so that a timing signal used for the testing may be varied.
摘要翻译：通过在通过电网连接的集成电路器件上使用测试电路来测试晶片上的集成电路器件。电网用于启用测试电路，并提供在晶片上仍能测试器件的能力。这样在分割部件之前便有助于在晶片中燃烧，因为不需要在各个集成电路器件上的接触点处单独建立电连接。在一个实施例中，可以调节振荡器的速度，以便可以通过改变测试电路的测试速度来进行进一步的测试。通过调整振荡器速度来确定不同工作速度下的集成电路的响应，从而可以改变用于测试的定时信号。

2. 发明授权

US5457400A Semiconductor array having built-in test circuit for wafer level testing 失效
标题翻译：具有晶圆级测试的内置测试电路的半导体阵列
公开(公告)号：US5457400A
公开(公告)日：1995-10-10
申请号：US96643
申请日：1993-07-23
申请人： Aftab Ahmad , Larren G. Weber , Robert S. Green
发明人： Aftab Ahmad , Larren G. Weber , Robert S. Green
IPC分类号： G01R31/30 , G06F11/27 , G01R31/28
CPC分类号： G01R31/30 , G06F11/27
摘要： A test circuit is provided for an integrated circuit device, whereby an oscillator is provided on-chip and is activated by a test circuit. The test circuit provides an ability to test the devices while still on the wafer and facilitates burning in the wafer prior to singulating the parts, since it is not necessary to separately establish electrical connections at contact points on the individual integrated circuit devices. The oscillator may be adjusted in speed so that further tests may be effected by changing a test speed through the test circuit. Response of the DUT at different operating speeds is determined by the adjustment of the oscillator speed so that a timing signal used for the testing may be varied.
摘要翻译：为集成电路器件提供了测试电路，由此在芯片上提供振荡器并由测试电路激活。测试电路提供了在仍然在晶片上测试器件的能力，并且在分离部件之前便于在晶片中燃烧，因为不需要在各个集成电路器件上的接触点处单独建立电连接。可以调节振荡器的速度，以便通过改变测试电路的测试速度来进一步测试。 DUT在不同工作速度下的响应由振荡器速度的调整决定，从而可以改变用于测试的定时信号。

3. 发明授权

US5241266A Built-in test circuit connection for wafer level burnin and testing of individual dies 失效
标题翻译：内置测试电路连接，用于晶圆级烧伤和单个模具测试
公开(公告)号：US5241266A
公开(公告)日：1993-08-31
申请号：US866622
申请日：1992-04-10
申请人： Aftab Ahmad , Larren G. Weber , Robert S. Green
发明人： Aftab Ahmad , Larren G. Weber , Robert S. Green
IPC分类号： G01R31/28
CPC分类号： G01R31/2856 , G01R31/2863
摘要： Integrated circuit devices are fabricated with an additional conductive layer deposited on a semiconductor wafer onto which the semiconductor devices have been formed. The additional layer provides a conductive path to power the test circuits and allows the use of very few electrical connections in order to permit testing of the devices while still on the wafer. The ability to test the devices while still on the wafer facilitates burning in the wafer prior to singulating the parts, since it is not necessary to establish electrical connections at contact points on the individual integrated circuit devices. In one embodiment of the invention, the additional conductive layer is a metal mask and in a further aspect of that embodiment permits external connections to be accomplished at locations outside the die areas, thereby avoiding damage to the integrated circuit devices. Subsequent to testing of the die in wafer form, the metal mask is stripped and the die may be singulated.
摘要翻译：集成电路器件由沉积在其上形成半导体器件的半导体晶片上的附加导电层制成。附加层为测试电路提供导通路径，并允许使用非常少的电连接，以便允许在仍在晶片上测试器件。由于不需要在单个集成电路器件上的接触点处建立电连接，所以在分离元件之前测试器件的能力在晶片上有助于刻蚀晶片。在本发明的一个实施例中，附加导电层是金属掩模，并且在该实施例的另一方面允许在管芯区域外部的位置实现外部连接，从而避免损坏集成电路器件。在以晶片形式测试模具之后，剥离金属掩模，并且可以将模具切割。

4. 发明授权

US07176549B2 Shallow trench isolation using low dielectric constant insulator 有权
标题翻译：使用低介电常数绝缘子的浅沟槽隔离
公开(公告)号：US07176549B2
公开(公告)日：2007-02-13
申请号：US11012012
申请日：2004-12-13
申请人： Klaus F. Schuegraf , Aftab Ahmad
发明人： Klaus F. Schuegraf , Aftab Ahmad
IPC分类号： H01L29/00
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the final isolation structure. Effective device isolation is achieved with a reduced trench depth by utilizing refilling dielectric materials having low dielectric constant.
摘要翻译：公开了一种浅沟槽隔离，其中沟槽深度减小到超过现有技术工艺中所达到的深度。减小的沟槽深度有助于在沟槽再填充过程期间消除空隙的形成，并且在最终隔离结构中提供更大的平坦度。通过利用具有低介电常数的再填充介电材料，通过减小沟槽深度实现有效的器件隔离。

5. 发明授权

US06930363B2 Barrier in gate stack for improved gate dielectric integrity 失效
标题翻译：栅极堆叠中的栅极，用于改善栅极电介质完整性
公开(公告)号：US06930363B2
公开(公告)日：2005-08-16
申请号：US10901552
申请日：2004-07-27
申请人： Nanseng Jeng , Aftab Ahmad
发明人： Nanseng Jeng , Aftab Ahmad
IPC分类号： H01L21/28 , H01L21/8234 , H01L29/49 , H01L29/94
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/823437
摘要： A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.
摘要翻译：公开了包含与杂质混合的硅的阻挡层，用于保护集成晶体管中的栅极电介质。特别地，阻挡层包括掺入氮的硅。在沉积期间可以将氮结合到栅极多晶硅的上部，或在硅沉积之后掺入氮的硅层。该层与CVD钨硅化物带结合是特别实用的。

6. 发明授权

US06770571B2 Barrier in gate stack for improved gate dielectric integrity 有权
标题翻译：栅极堆叠中的栅极，用于改善栅极电介质完整性
公开(公告)号：US06770571B2
公开(公告)日：2004-08-03
申请号：US10339731
申请日：2003-01-08
申请人： Nanseng Jeng , Aftab Ahmad
发明人： Nanseng Jeng , Aftab Ahmad
IPC分类号： H01L2131
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/823437
摘要： A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.
摘要翻译：公开了包含与杂质混合的硅的阻挡层，用于保护集成晶体管中的栅极电介质。特别地，阻挡层包括掺入氮的硅。在沉积期间可以将氮结合到栅极多晶硅的上部，或在硅沉积之后掺入氮的硅层。该层与CVD钨硅化物带结合是特别实用的。

7. 发明授权

US06743979B1 Bonding pad isolation 有权
标题翻译：粘接垫隔离
公开(公告)号：US06743979B1
公开(公告)日：2004-06-01
申请号：US10652453
申请日：2003-08-29
申请人： Michael J. Berman , Aftab Ahmad , Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
发明人： Michael J. Berman , Aftab Ahmad , Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
IPC分类号： H05K506
CPC分类号： H01L24/06 , H01L24/05 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48463 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2224/45099 , H01L2924/00012
摘要： An integrated circuit, including a substrate with circuitry formed therein, where the substrate has a peripheral edge. Also included are a top most electrically conductive layer and an underlying electrically conductive layer. Outer bonding pads are disposed in an outer ring, and are formed within the top most layer. Inner bonding pads are disposed in an inner ring, and are formed within the top most layer. Inner connectors electrically connect the inner bonding pads to the circuitry. The inner connectors are formed within the underlying layer, and have a width that is less than the width of the inner bonding pads, thereby defining a gap between the inner connectors. Outer connectors electrically connect the outer bonding pads to the circuitry. The outer connectors are formed within the underlying layer, and have a width that is less than the width of the gap between the inner connectors.
摘要翻译：一种集成电路，包括其中形成有电路的衬底，其中衬底具有外围边缘。还包括最顶层的导电层和底层导电层。外部接合焊盘设置在外圈中，并形成在最上层。内部接合焊盘设置在内圈中，并且形成在最顶层内。内部连接器将内部接合焊盘电连接到电路。内部连接器形成在下面的层中，并且具有小于内部焊盘的宽度的宽度，由此限定内部连接器之间的间隙。外部连接器将外部接合焊盘电连接到电路。外部连接器形成在下面的层中，并且具有小于内部连接器之间的间隙的宽度的宽度。

8. 发明授权

US06373114B1 Barrier in gate stack for improved gate dielectric integrity 有权
标题翻译：栅极堆叠中的栅极，用于改善栅极电介质完整性
公开(公告)号：US06373114B1
公开(公告)日：2002-04-16
申请号：US09178306
申请日：1998-10-23
申请人： Nanseng Jeng , Aftab Ahmad
发明人： Nanseng Jeng , Aftab Ahmad
IPC分类号： H01L2994
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/823437
摘要： A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.
摘要翻译：公开了包含与杂质混合的硅的阻挡层，用于保护集成晶体管中的栅极电介质。特别地，阻挡层包括掺入氮的硅。在沉积期间可以将氮结合到栅极多晶硅的上部，或在硅沉积之后掺入氮的硅层。该层与CVD钨硅化物带结合是特别实用的。

9. 发明授权

US06281092B1 Method for manufacturing a metal-to-metal capacitor utilizing only one masking step 有权
标题翻译：仅使用一个掩模步骤来制造金属 - 金属电容器的方法
公开(公告)号：US06281092B1
公开(公告)日：2001-08-28
申请号：US09347487
申请日：1999-07-02
申请人： Aftab Ahmad
发明人： Aftab Ahmad
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L21/3212
摘要： A capacitor is fabricated on a semiconductor substrate by first forming a first capacitor electrode on the semiconductor substrate and forming a planar insulating layer over the first capacitor electrode. A photoresist layer is then formed over the planar insulating layer and patterned utilizing in only masking step to form an opening over the first capacitor electrode. Through the opening, the planar insulating layer is etched, and a capacitor dielectric layer is thereafter formed. A second capacitor electrode is then formed over the capacitor dielectric layer in alignment with the first capacitor electrode. The structure is planarized to expose the planar insulating layer. In a preferred embodiment, a trench in the second capacitor electrode is protected during planarization by a spin-on photoresist that is stripped following planarization.
摘要翻译：在半导体衬底上制造电容器，首先在半导体衬底上形成第一电容器电极，并在第一电容器电极上形成平面绝缘层。然后在平面绝缘层上形成光致抗蚀剂层，并且仅在掩模步骤中利用图案化以在第一电容器电极上形成开口。通过开口蚀刻平面绝缘层，然后形成电容器电介质层。然后在电容器电介质层上形成与第一电容器电极对准的第二电容器电极。将该结构平坦化以暴露平面绝缘层。在优选实施例中，第二电容器电极中的沟槽在平坦化期间通过在平坦化之后剥离的旋涂光致抗蚀剂被保护。

10. 发明授权

US6046472A Graded LDD implant process for sub-half-micron MOS devices 失效
公开(公告)号：US6046472A
公开(公告)日：2000-04-04
申请号：US949997
申请日：1997-10-14
申请人： Aftab Ahmad , Charles Dennison
发明人： Aftab Ahmad , Charles Dennison
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L29/784
CPC分类号： H01L29/6659 , H01L21/28247 , H01L21/823814 , H01L29/1083 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , Y10S257/90 , Y10S257/917
摘要： A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N- LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

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