专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140093245A1 OPTICAL IO INTERCONNECT HAVING A WDM ARCHITECTURE AND CDR CLOCK SHARING RECEIVER 有权
标题翻译：具有WDM架构和CDR时钟共享接收器的光纤IO互连
公开(公告)号：US20140093245A1
公开(公告)日：2014-04-03
申请号：US13629945
申请日：2012-09-28
申请人： Inho Kim , Zuoguo Wu
发明人： Inho Kim , Zuoguo Wu
IPC分类号： H04J14/02
CPC分类号： H04B10/69 , H04B10/40 , H04B10/801 , H04J14/02 , H04L7/00 , H04L25/14
摘要： Systems and methods may provide for an optical module including an optical demultiplexer to receive a wavelength division multiplexed (WDM) signal from a single receive optical fiber and separate the WDM signal into a plurality of optical signals. Additionally, the optical module may include a receiver conversion unit to convert the plurality of optical signals into a corresponding plurality of electrical signals. In addition, the optical module may include a buffer chip having a single clock and data recovery (CDR) module to recover a clock from a designated signal in the plurality of electrical signals and distribute the recovered clock to a plurality of data lanes corresponding to the plurality of electrical signals.
摘要翻译：系统和方法可以提供包括光解复用器的光模块，以从单个接收光纤接收波分复用（WDM）信号，并将WDM信号分离成多个光信号。另外，光学模块可以包括将多个光信号转换为对应的多个电信号的接收机转换单元。另外，光学模块可以包括具有单个时钟和数据恢复（CDR）模块的缓冲器芯片，以从多个电信号中的指定信号中恢复时钟，并将恢复的时钟分配给多个对应于多个电信号。

2. 发明申请

US20060215787A1 Data receiver including a transconductance amplifier 有权
标题翻译：数据接收机包括跨导放大器
公开(公告)号：US20060215787A1
公开(公告)日：2006-09-28
申请号：US11091227
申请日：2005-03-28
申请人： Zuoguo Wu , Feng Chen
发明人： Zuoguo Wu , Feng Chen
IPC分类号： H04L27/00
CPC分类号： H04L27/0002 , H03F3/45183 , H03F3/45968
摘要： According to one embodiment, a system, apparatus, and method for receiving high-speed signals using a receiver with a transconductance amplifier is presented. The apparatus comprises a transconductance amplifier to receive input voltage derived from an input signal, a clocked current comparator to receive output current from the transconductance amplifier, and a storage element to receive a binary value from the clocked current comparator.
摘要翻译：根据一个实施例，提出了一种使用具有跨导放大器的接收机来接收高速信号的系统，装置和方法。该装置包括跨导放大器以接收从输入信号导出的输入电压，时钟电流比较器以接收来自跨导放大器的输出电流，以及存储元件以从时钟电流比较器接收二进制值。

3. 发明申请

US20220222198A1 SIDEBAND INTERFACE FOR DIE-TO-DIE INTERCONNECTS 有权
公开(公告)号：US20220222198A1
公开(公告)日：2022-07-14
申请号：US17708367
申请日：2022-03-30
申请人： Narasimha Lanka , Swadesh Choudhary , Debendra Das Sharma , Lakshmipriya Seshan , Zuoguo Wu , Gerald Pasdast
发明人： Narasimha Lanka , Swadesh Choudhary , Debendra Das Sharma , Lakshmipriya Seshan , Zuoguo Wu , Gerald Pasdast
IPC分类号： G06F13/42 , H01L25/065 , H01L23/538 , G06F13/40
摘要： In one embodiment, an apparatus includes: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry; and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry may include: a first sideband data receiver to couple to a first sideband data lane and a first sideband clock receiver to couple to a first sideband clock lane; and a second sideband data receiver to couple to a second sideband data lane and a second sideband clock receiver to couple to a second sideband clock lane. The physical layer circuitry may assign a functional sideband comprising: one of the first or second sideband data lanes; and one of the first or second sideband clock lanes. Other embodiments are described and claimed.

4. 发明申请

US20090245416A1 INPUT/OUTPUT DRIVER SWING CONTROL AND SUPPLY NOISE REJECTION 有权
标题翻译：输入/输出驱动器控制和供电噪声抑制
公开(公告)号：US20090245416A1
公开(公告)日：2009-10-01
申请号：US12060251
申请日：2008-03-31
申请人： Zuoguo Wu , Feng Chen , Sanjay Dabral
发明人： Zuoguo Wu , Feng Chen , Sanjay Dabral
IPC分类号： H04L25/49
CPC分类号： H04L25/0276
摘要： In general, in one aspect, the disclosure describes an apparatus having an averager to receive differential output voltages of a transmitter and generate an average transmitter output voltage. A comparator is to compare the average transmitter output voltage to a reference voltage and generate a difference therebetween. An integrator is to integrate the difference between the average transmitter output voltage and the reference voltage over time. The integrated difference is fed back to the transmitter to bias the transmitter.
摘要翻译：通常，在一个方面，本公开描述了一种具有平均器以接收发射机的差分输出电压并产生平均发射机输出电压的装置。比较器将平均发射机输出电压与参考电压进行比较，并产生它们之间的差值。积分器将整合平均发射机输出电压和参考电压随时间的差异。积分差值被反馈给发射机以偏置发射机。

5. 发明授权

US07579905B2 Reduced jitter amplification methods and apparatuses 有权
标题翻译：减少抖动放大方法和装置
公开(公告)号：US07579905B2
公开(公告)日：2009-08-25
申请号：US11714637
申请日：2007-03-05
申请人： Zuoguo Wu
发明人： Zuoguo Wu
IPC分类号： G06G7/12
CPC分类号： H03F1/3211 , G11C7/02 , G11C7/22 , G11C7/225 , H03F3/45183 , H03F2203/45342 , H03F2203/45454 , H03F2203/45511 , H03F2203/45626 , H03F2203/45641
摘要： Apparatuses, circuits, and methods to amplify signals with reduced jitter are disclosed. Embodiments generally comprise amplifiers coupled with apparatuses that adjust peak frequencies of the amplifiers to reduce jitter. In many system and apparatus embodiments, the frequency gain boosters receive one or more feedback signals derived from input signals applied to the amplifiers. The frequency gain boosters generally respond to the feedback signals by manipulating or controlling active loads coupled to the amplifiers. In controlling the active loads, the frequency gain boosters generally cause the active loads to peak at frequencies at or near the input signals, the result being attenuated jitter in an output signal of the amplifier.
摘要翻译：公开了以减少抖动放大信号的装置，电路和方法。实施例通常包括与调节放大器的峰值频率以减少抖动的装置耦合的放大器。在许多系统和装置实施例中，频率增益增强器接收从施加到放大器的输入信号导出的一个或多个反馈信号。频率增益增强器通常通过操纵或控制耦合到放大器的有源负载来响应反馈信号。在控制有源负载时，频率增益增强器通常使有源负载在输入信号处或附近的频率处达到峰值，结果是在放大器的输出信号中衰减了抖动。

6. 发明申请

US20080218254A1 Reduced jitter amplification methods and apparatuses 有权
标题翻译：减少抖动放大方法和装置
公开(公告)号：US20080218254A1
公开(公告)日：2008-09-11
申请号：US11714637
申请日：2007-03-05
申请人： Zuoguo Wu
发明人： Zuoguo Wu
IPC分类号： H03B1/00
CPC分类号： H03F1/3211 , G11C7/02 , G11C7/22 , G11C7/225 , H03F3/45183 , H03F2203/45342 , H03F2203/45454 , H03F2203/45511 , H03F2203/45626 , H03F2203/45641
摘要： Apparatuses, circuits, and methods to amplify signals with reduced jitter are disclosed. Embodiments generally comprise amplifiers coupled with apparatuses that adjust peak frequencies of the amplifiers to reduce jitter. In many system and apparatus embodiments, the frequency gain boosters receive one or more feedback signals derived from input signals applied to the amplifiers. The frequency gain boosters generally respond to the feedback signals by manipulating or controlling active loads coupled to the amplifiers. In controlling the active loads, the frequency gain boosters generally cause the active loads to peak at frequencies at or near the input signals, the result being attenuated jitter in an output signal of the amplifier.
摘要翻译：公开了以减少抖动放大信号的装置，电路和方法。实施例通常包括与调节放大器的峰值频率以减少抖动的装置耦合的放大器。在许多系统和装置实施例中，频率增益增强器接收从施加到放大器的输入信号导出的一个或多个反馈信号。频率增益增强器通常通过操纵或控制耦合到放大器的有源负载来响应反馈信号。在控制有源负载时，频率增益增强器通常使有源负载在输入信号处或附近的频率处达到峰值，结果是在放大器的输出信号中衰减了抖动。

7. 发明申请

US20080204097A1 INVERTER BASED DUTY CYCLE CORRECTION APPARATUSES AND SYSTEMS 有权
标题翻译：基于变频器的占空比校正装置和系统
公开(公告)号：US20080204097A1
公开(公告)日：2008-08-28
申请号：US11680614
申请日：2007-02-28
申请人： Zuoguo Wu
发明人： Zuoguo Wu
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K3/356104
摘要： Apparatuses, circuits, and methods to reduce duty cycle errors are disclosed. Embodiments generally comprise buffer circuits coupled with error detection circuits and correction feedback circuits that sense duty cycles errors in output signals from the buffer circuits, generate error signals, and couple the error signals back to the inputs to correct or reduce the duty cycle errors. The error circuits may comprise active low pass filters in various embodiments, while amplifiers generally comprise inverter buffers or other simple buffers which alter or affect the input signals to the buffer circuits in order to reduce the duty cycle errors. In many system and apparatus embodiments, the error circuits comprise a resistor-capacitor circuit coupled with an inverter buffer. The error detection circuits generally function as active low pass filters and generate error signals for the feedback circuits.
摘要翻译：公开了减少占空比误差的装置，电路和方法。实施例通常包括与错误检测电路和校正反馈电路耦合的缓冲电路，校正反馈电路检测来自缓冲电路的输出信号中的占空比误差，产生误差信号，并将误差信号耦合回输入以校正或减少占空比误差。在各种实施例中，误差电路可以包括有源低通滤波器，而放大器通常包括反相缓冲器或其它简单缓冲器，其改变或影响到缓冲器电路的输入信号，以便减少占空比误差。在许多系统和装置实施例中，误差电路包括与反相缓冲器耦合的电阻 - 电容电路。误差检测电路通常用作有源低通滤波器，并产生反馈电路的误差信号。

8. 发明申请

US20220261308A1 VALID SIGNAL FOR LATENCY SENSITIVE DIE-TO-DIE (D2D) INTERCONNECTS 有权
公开(公告)号：US20220261308A1
公开(公告)日：2022-08-18
申请号：US17733627
申请日：2022-04-29
申请人： Narasimha Lanka , Debendra Das Sharma , Lakshmipriya Seshan , Swadesh Choudhary , Zuoguo Wu , Gerald Pasdast
发明人： Narasimha Lanka , Debendra Das Sharma , Lakshmipriya Seshan , Swadesh Choudhary , Zuoguo Wu , Gerald Pasdast
IPC分类号： G06F11/10 , G06F11/07 , G06F13/40
摘要： Embodiments herein relate to a die of a multi-die package, wherein the die is coupled with another die via a die-to-die (D2D) interconnect link. The die may transmit a data signal to the other die via a data lane of the D2D interconnect link. The die may further transmit, concurrently with the data signal, a valid signal to the other die via a valid lane of the D2D interconnect link. The valid signal may change logical state at least once during the transmission of the data signal. Other embodiments may be described and claimed.

9. 发明授权

US09536863B2 Interconnection of a packaged chip to a die in a package utilizing on-package input/output interfaces 有权
标题翻译：使用封装输入/输出接口将封装芯片与封装中的管芯互连
公开(公告)号：US09536863B2
公开(公告)日：2017-01-03
申请号：US13994919
申请日：2011-12-22
申请人： Todd A. Hinck , Zuoguo Wu , Aaron Martin , Andrew W. Martwick , John B. Halbert
发明人： Todd A. Hinck , Zuoguo Wu , Aaron Martin , Andrew W. Martwick , John B. Halbert
IPC分类号： G06F13/12 , G06F13/38 , H01L25/065 , H04B1/40 , H01L23/538 , H01L23/48 , H01L23/66 , H01L25/11
CPC分类号： H01L25/0655 , G06F13/385 , H01L23/48 , H01L23/5383 , H01L23/66 , H01L25/115 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H04B1/40 , Y02D10/14 , Y02D10/151 , H01L2224/0401
摘要： Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme. A second set of single-ended receiver circuits is included on a third die. The receiver circuits have termination. Conductive lines are coupled between the second set of transmitter circuits and the second set of receiver circuits. The lengths of the conductive lines are matched and the second set of receiver circuits is disposed within a second package.
摘要翻译：用于互连集成电路管芯的装置。第一组单端发射机电路包括在第一裸片上。发射机电路阻抗匹配，无均衡。第一组单端接收器电路包括在第二管芯上。接收器电路没有终端，没有均衡。导电线耦合在第一组发射器电路和第一组接收器电路之间。导线的长度相匹配。第一芯片，第一组单端发射机电路，第二芯片，第一组单端接收器电路和导线布置在第一封装内。第一组芯片包括第二组单端发射机电路。发射机电路阻抗匹配，无均衡。根据数据总线反转（DBI）方案发送从第二组发射机电路发送的数据。第三组裸片包括第二组单端接收机电路。接收器电路具有端接。导电线耦合在第二组发射器电路和第二组接收器电路之间。导线的长度匹配，第二组接收器电路设置在第二封装内。

10. 发明申请

US20130313709A1 INTERCONNECTION OF A PACKAGED CHIP TO A DIE IN A PACKAGE UTILIZING ON-PACKAGE INPUT/OUTPUT INTERFACES 有权
标题翻译：使用包装输入/输出接口的包装中的包装芯片的互连
公开(公告)号：US20130313709A1
公开(公告)日：2013-11-28
申请号：US13994919
申请日：2011-12-22
申请人： Todd A. Hinck , Zuoguo Wu , Aaron Martin , Andrew W. Martwick , John B. Halbert
发明人： Todd A. Hinck , Zuoguo Wu , Aaron Martin , Andrew W. Martwick , John B. Halbert
IPC分类号： H01L25/065
CPC分类号： H01L25/0655 , G06F13/385 , H01L23/48 , H01L23/5383 , H01L23/66 , H01L25/115 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H04B1/40 , Y02D10/14 , Y02D10/151 , H01L2224/0401
摘要： Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme. A second set of single-ended receiver circuits is included on a third die. The receiver circuits have termination. Conductive lines are coupled between the second set of transmitter circuits and the second set of receiver circuits. The lengths of the conductive lines are matched and the second set of receiver circuits is disposed within a second package.
摘要翻译：用于互连集成电路管芯的装置。第一组单端发射机电路包括在第一裸片上。发射机电路阻抗匹配，无均衡。第一组单端接收器电路包括在第二管芯上。接收器电路没有终端，没有均衡。导电线耦合在第一组发射器电路和第一组接收器电路之间。导线的长度相匹配。第一芯片，第一组单端发射机电路，第二芯片，第一组单端接收器电路和导线布置在第一封装内。第一组芯片包括第二组单端发射机电路。发射机电路阻抗匹配，无均衡。根据数据总线反转（DBI）方案发送从第二组发射机电路发送的数据。第三组裸片包括第二组单端接收机电路。接收器电路具有端接。导电线耦合在第二组发射器电路和第二组接收器电路之间。导线的长度匹配，第二组接收器电路设置在第二封装内。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式