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    • 1. 发明授权
      US06265253B1 Aluminum disposable spacer to reduce mask count in CMOS transistor formation 有权
    • Aluminum disposable spacer to reduce mask count in CMOS transistor formation
    • 铝一次性间隔物，以减少CMOS晶体管形成中的掩模数量
    • US06265253B1
    • 2001-07-24
    • US09305098
    • 1999-05-05
    • Todd Lukanc , Matthew S. Buynoski , Zicheng Gary Ling
    • Todd Lukanc , Matthew S. Buynoski , Zicheng Gary Ling
    • H01L218238
    • H01L21/823864
    • Semiconductor devices of different conductivity types with optimized junction locations are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, sidewall spacers on side surfaces of the gates, and aluminum disposable spacers on the sidewall spacers. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the aluminum disposable spacers on the sidewall spacers on the unmasked gates removed, and lightly or moderately doped source/drain extension implants of the second impurity type formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining aluminum disposable spacers removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. By using aluminum disposable spacers, which can be easily formed and removed without damage to other structures on the substrate, the critical masking steps for source/drain ion implantation are reduced to two, thereby reducing production costs and increasing manufacturing throughput. By employing sidewall spacers, impurities are prevented from being implanted at the edges of the gates. Thus, when source/drain junctions are formed, as by heating and diffusing the implanted impurities, they are advantageously located proximal to the gate edges, and not under the gates, thereby improving device performance.
    • 具有优化的连接位置的不同导电类型的半导体器件使用最少数量的临界掩模形成在半导体衬底上。 实施例包括在半导体衬底的主表面上形成导电栅极，在栅极的侧表面上的侧壁间隔物和侧壁间隔物上的铝一次性间隔物。 然后在主要表面的浇口和部分上形成光致抗蚀剂掩模，以便植入第一导电类型的杂质。 然后在衬底中形成第二杂质类型的中等或重的源/漏植入物，去除未屏蔽的栅极上的侧壁间隔物上的铝一次性间隔物，并且形成第二杂质类型的轻或中等掺杂的源极/漏极延伸植入物 底物。 然后去除第一掩模，并且在主表面的先前未覆盖的浇口和注入部分上形成第二光致抗蚀剂掩模。 然后形成具有第一导电类型的杂质的中等或重的源极/漏极植入物，去除剩余的铝一次性间隔物，并形成第一导电类型的轻度或中度掺杂的源极/漏极延伸植入物。 通过使用可以容易地形成和去除的铝一次性间隔件，而不损坏衬底上的其它结构，源/漏离子注入的关键掩蔽步骤减少到两个，从而降低生产成本并提高制造生产量。 通过使用侧壁间隔物，防止杂质被植入门的边缘。 因此，当形成源极/漏极结时，通过加热和扩散植入的杂质，它们有利地位于栅极边缘附近，而不在栅极下方，从而提高器件性能。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US06221706B1 Aluminum disposable spacer to reduce mask count in CMOS transistor formation 失效
    • Aluminum disposable spacer to reduce mask count in CMOS transistor formation
    • 铝一次性间隔物，以减少CMOS晶体管形成中的掩模数量
    • US06221706B1
    • 2001-04-24
    • US09268713
    • 1999-03-17
    • Todd Lukanc , Raymond T. Lee , Zicheng Gary Ling , Matthew S. Buynoski
    • Todd Lukanc , Raymond T. Lee , Zicheng Gary Ling , Matthew S. Buynoski
    • H01L218238
    • H01L21/823864
    • MOS semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable aluminum sidewall spacers on the side surfaces of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the aluminum sidewall spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining aluminum sidewall spacers are removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. By using disposable aluminum sidewall spacers, which can be easily formed and removed without damage to other structures on the substrate or to the substrate silicon, the critical masking steps for source/drain ion implantation can be reduced to two, thereby reducing production costs and increasing manufacturing throughput.
    • 使用最少数量的临界掩模，在半导体衬底上形成不同导电类型的MOS半导体器件。 实施例包括在半导体衬底的主表面上形成导电栅极和在栅极的侧表面上的一次性铝侧壁间隔物。 然后在主要表面的浇口和部分上形成光致抗蚀剂掩模，以便植入第一导电类型的杂质。 然后在衬底中形成第二杂质类型的中等或重的源/漏植入物，然后去除未屏蔽的栅极上的铝侧壁间隔物，并且在第二杂质类型中形成轻度或中度掺杂的第二杂质类型的源极/漏极延伸植入物 基质。 然后去除第一掩模，并且在主表面的先前未覆盖的浇口和注入部分上形成第二光致抗蚀剂掩模。 然后形成具有第一导电类型的杂质的中等或重的源/漏植入物，除去剩余的铝侧壁间隔物，形成第一导电类型的轻度或中度掺杂的源极/漏极延伸植入物。 通过使用可以容易地形成和去除而不损坏衬底或衬底硅上的其它结构的一次性铝侧壁间隔物，用于源/漏离子注入的关键掩蔽步骤可以减少到两个，从而降低生产成本并增加 制造吞吐量。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US06868537B1 Method of generating an IC mask using a reduced database 有权
    • Method of generating an IC mask using a reduced database
    • 使用简化数据库生成IC掩模的方法
    • US06868537B1
    • 2005-03-15
    • US10082991
    • 2002-02-25
    • Jonathan J. Ho , Xin X. Wu , Zicheng Gary Ling , Jan L. de Jong
    • Jonathan J. Ho , Xin X. Wu , Zicheng Gary Ling , Jan L. de Jong
    • G03F1/14 , G06F17/50
    • G03F1/36 , G03F1/68 , G06F17/5068 , G06F2217/12
    • For IC devices that have repeating structures, a method of generating a database for making a mask layer starts with a hierarchical database describing at least one repeating element in the layer, a skeleton that surrounds the repeating elements, and instructions as to where to locate the repeating elements within the skeleton. This database is modified to generate a database that has optical proximity correction (OPC) for diffraction of light that will pass through the mask and expose photoresist on the IC layer. The optical-proximity corrected mask database is fractured by a mask house using instructions on how the modified data base will be divided to form repeating elements that are still identical after OPC, a mask skeleton that includes non-repeating elements, and instructions for placement of the repeating elements in the skeleton. Thus the resulting mask database is smaller than a mask database that includes all copies of repeating elements.
    • 对于具有重复结构的IC设备，生成用于制作掩模层的数据库的方法从描述层中的至少一个重复元素的分层数据库开始，围绕重复元素的骨架以及关于在哪里定位的指令 重复骨骼内的元素。 该数据库被修改以产生具有光学邻近校正（OPC）的数据库，用于衍射通过掩模并在IC层上曝光光致抗蚀剂的光的衍射。 使用关于如何将经修改的数据库分割以形成在OPC之后仍然相同的重复元素的指令，包含非重复元素的掩码框架以及用于放置 骨骼中的重复元素。 因此，所得到的掩码数据库小于包含所有重复元素副本的掩码数据库。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US06479350B1 Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers 失效
    • Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers
    • 减少屏蔽步骤使用可移动的非晶硅侧壁间隔物形成CMOS晶体管
    • US06479350B1
    • 2002-11-12
    • US09639814
    • 2000-08-17
    • Zicheng Gary Ling , Todd Lukanc , Raymond T. Lee
    • Zicheng Gary Ling , Todd Lukanc , Raymond T. Lee
    • H01L21336
    • H01L29/6653 , H01L21/823814 , H01L21/823864
    • CMOS semiconductor devices comprising MOS transistors of different channel conductivity type are formed in or on a common semiconductor substrate using a minimum number of critical masks. Embodiments include forming conductive gate/insulator layer stacks on spaced-apart, different conductivity portions of the main surface of the substrate, forming etch-resistant inner sidewall spacers on side surfaces of the layer stacks, and forming easily etched, amorphous semiconductor disposable outer sidewall spacers on the inner sidewall spacers. The use of disposable outer sidewall spacers allows heavy and light source/drain implantations of opposite conductivity type to be performed for forming PMOS and NMOS transistors with the use of only two critical masks, thereby reducing production cost and duration, while increasing manufacturing throughput.
    • 包含不同沟道导电类型的MOS晶体管的CMOS半导体器件使用最少数量的临界掩模形成在公共半导体衬底中或上。 实施例包括在衬底的主表面的间隔开的不同导电部分上形成导电栅极/绝缘体层堆叠，在层堆叠的侧表面上形成耐腐蚀的内侧壁间隔物，以及形成容易蚀刻的非晶半导体一次性外侧壁 内侧壁间隔件上的间隔件。 使用一次性外侧壁间隔件可以实现相反导电类型的重和光源/漏极注入，以便仅使用两个临界掩模来形成PMOS和NMOS晶体管，从而降低生产成本和持续时间，同时提高制造吞吐量。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US06287904B1 Two step mask process to eliminate gate end cap shortening 有权
    • Two step mask process to eliminate gate end cap shortening
    • 两步掩模过程，以消除门帽缩短
    • US06287904B1
    • 2001-09-11
    • US09499047
    • 2000-02-07
    • Raymond T. Lee , Zicheng Gary Ling
    • Raymond T. Lee , Zicheng Gary Ling
    • H01L21336
    • H01L29/4238 , H01L21/28123
    • Metal oxide semiconductor devices are formed having gates with minimum endcap width and no source/drain leakage. A pair of source/drain regions is formed in a substrate, and a gate oxide is formed on the substrate. A layer of a conductive material, such as polysilicon, is formed on the gate oxide layer, masked and etched to form an extended-width gate having endcaps of a greater width than the endcap design rules. A second mask is formed to cover the extended-width gate up to the desired width of the endcaps (i.e., the design width) and to expose the portions of the extended-width gate beyond the endcap design width. The exposed portions of the extended-width gate are then etched, resulting in a completed gate having endcaps of the design width. Since the endcaps are initially formed to a greater width than the design width, any pullback that occurs during printing of the mask or etching of the gate does not cause the gate to be insufficiently wide to avoid source/drain leakage. Since the excess endcap material is removed, adjacent features and/or devices can be densely spaced on the substrate.
    • 金属氧化物半导体器件形成为具有最小端盖宽度且没有源漏漏极的栅极。 在衬底中形成一对源极/漏极区，并且在衬底上形成栅极氧化物。 在栅极氧化物层上形成诸如多晶硅的导电材料层，被掩模和蚀刻以形成具有比端盖设计规则更大宽度的端盖的延伸宽度门。 形成第二掩模以将延伸宽度的栅极覆盖直到端盖的期望宽度（即，设计宽度），并且将扩展宽度栅极的部分暴露超过端盖设计宽度。 然后对扩展宽度栅极的暴露部分进行蚀刻，得到具有设计宽度的端盖的完成的栅极。 由于端盖最初形成为比设计宽度更大的宽度，所以在印刷掩模或蚀刻栅极期间发生的任何回退都不会导致栅极不够宽以避免源/漏泄漏。 由于去除多余的端盖材料，相邻的特征和/或器件可以在基底上密集地间隔开。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US06306702B1 Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length 有权
    • Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length
    • 具有基本上相同的0.25微米栅极长度的CMOS晶体管的双间隔法
    • US06306702B1
    • 2001-10-23
    • US09379627
    • 1999-08-24
    • Ming Yin Hao , Richard P. Rouse , Zicheng Gary Ling
    • Ming Yin Hao , Richard P. Rouse , Zicheng Gary Ling
    • H01L218238
    • H01L21/823864 , H01L21/823814
    • CMOS transistors, i.e., N- and P-type transistors, are formed with substantially the same gate length and source/drain regions with lightly doped extensions. Embodiments include sequentially: ion implanting an N-type impurity, e.g. As, to form the N- type transistor shallow source/drain implants; forming relatively thin first sidewall spacers on the gates of both transistors; ion implanting a P-type impurity, e.g. BF2, to form shallow source/drain extension implants for the P-type transistor; forming relatively thick side wall spacers on the first sidewall spacers of both transistors; ion implanting, e.g. As, to form moderately or heavily doped N-type implants; activation annealing at a first temperature, e.g., about 1050° C. to form the shallow N- and P-type source/drain extensions and moderately or heavily doped P-type source/drain regions; ion implanting a P-type impurity, e.g., BF2, to form moderately or heavily doped P-type source/drain implants; and activation annealing at a second temperature less than the first temperature, e.g., at about 1000° C. to form moderately or heavily doped P type source/drain regions.
    • CMOS晶体管，即N型和P型晶体管形成为具有基本上相同的栅极长度和具有轻掺杂扩展的源极/漏极区域。 实施方案包括顺序地：离子注入N型杂质，例如 为了形成N型晶体管浅源/漏植入物; 在两个晶体管的栅极上形成较薄的第一侧壁间隔物; 离子注入P型杂质。 BF2，形成P型晶体管的浅源极/漏极延伸注入; 在两个晶体管的第一侧壁间隔物上形成相对厚的侧壁间隔物; 离子注入 为了形成适度或重掺杂的N型植入物; 在第一温度例如约1050℃下进行活化退火以形成浅的N和P型源极/漏极延伸部分和适度或重掺杂的P型源极/漏极区域; 离子注入P型杂质例如BF 2，以形成适度或重掺杂的P型源极/漏极植入物; 以及在小于第一温度的第二温度例如约1000℃下进行活化退火，以形成适度或重掺杂的P型源/漏区。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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