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1. 发明授权

US08479130B1 Method of designing integrated circuit that accounts for device aging 有权
标题翻译：设计集成电路设计老化的方法
公开(公告)号：US08479130B1
公开(公告)日：2013-07-02
申请号：US13607787
申请日：2012-09-09
申请人： Zhichen Zhang , Chuanzheng Wang
发明人： Zhichen Zhang , Chuanzheng Wang
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5045 , G06F2217/76 , G06F2217/80
摘要： A method of designing an integrated circuit (IC) includes simulating aging evolution of the IC by providing a standard cells library, and a device activity file of device electrical activity in the standard cells as a function of electrical activity at the pins of the standard cells, taking into account Hot Carrier Injection, Negative Bias Temperature Instability, and gate oxide breakdown. A standard cell evolution file is provided that stores electrical characteristic aging data of standard cells. An instance activity file is provided of simulated electrical activity at the pins of individual instances of the cells in the IC. The instance activity file and the device activity file are used to analyze device activity and consequent aging evolution of the devices, and then generate data for consequent aging evolution of the IC. The IC design can then be modified to account for the aging evolution.
摘要翻译：设计集成电路（IC）的方法包括通过提供标准单元库来模拟IC的老化演变，以及标准单元中器件电活动的器件活动文件作为标准单元的引脚上的电活动的函数，考虑到热载体注入，负偏压温度不稳定性和栅极氧化物分解。提供标准单元演化文件，其存储标准单元的电特性老化数据。在IC中的单元的各个实例的引脚处提供了模拟电活动的实例活动文件。实例活动文件和设备活动文件用于分析设备的活动和随后的设备老化演变，然后生成数据，以便随后的IC老化演变。然后可以修改IC设计以解释老化进化。

2. 发明申请

US20150234961A1 METHOD AND APPARATUS FOR CIRCUIT RELIABILITY AGING 审中-公开
标题翻译：电路可靠性老化的方法与装置
公开(公告)号：US20150234961A1
公开(公告)日：2015-08-20
申请号：US14558694
申请日：2014-12-02
申请人： Zhichen Zhang , Xavier Hours , Mehul D. Shroff , Chuanzheng Wang , Qilin Zhang
发明人： Zhichen Zhang , Xavier Hours , Mehul D. Shroff , Chuanzheng Wang , Qilin Zhang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/76
摘要： A method for integrated circuit reliability aging simulation includes dividing a target time period into N stages including a first stage and a second stage; obtaining first parameter values of a reliability model for the first stage; performing a first simulation on the circuit based on the reliability model and the first parameter values to obtain first aging results; obtaining second parameter values of the reliability model for the second stage; and performing a second simulation on the circuit based on the reliability model and the second parameter values to obtain second aging results.
摘要翻译：一种用于集成电路可靠性老化模拟的方法，包括将目标时间段划分为包括第一阶段和第二阶段的N个阶段; 获得第一阶段的可靠性模型的第一参数值; 基于可靠性模型和第一参数值在电路上执行第一模拟以获得第一老化结果; 获得第二阶段的可靠性模型的第二参数值; 以及基于所述可靠性模型和所述第二参数值在所述电路上执行第二仿真以获得第二老化结果。

3. 发明授权

US09222968B2 Monitoring system for detecting degradation of integrated circuit 有权
标题翻译：用于检测集成电路劣化的监控系统
公开(公告)号：US09222968B2
公开(公告)日：2015-12-29
申请号：US14076286
申请日：2013-11-11
申请人： Zhichen Zhang , Chuanzheng Wang , Qilin Zhang
发明人： Zhichen Zhang , Chuanzheng Wang , Qilin Zhang
IPC分类号： G01R31/02 , G01R31/28 , G01R31/27
CPC分类号： G01R31/2856 , G01R31/275 , G01R31/2849
摘要： A monitoring system for detecting stress degradation of a semiconductor integrated circuit has an amplifier circuit and degradation test transistors. Multiplexers are provided that have an output coupled to a respective electrode of the degradation test transistor. Each of the multiplexers has an input coupled to one of the monitor nodes and a respective node of the amplifier circuit. In operation, the multiplexers selectively insert the degradation test transistor into either the integrated circuit or the amplifier circuit so that when inserted into the integrated circuit the degradation test transistor is subjected to stress degradation voltages in the integrated circuit. When the degradation test transistor is inserted into the amplifier circuit, an output signal is generated that is indicative of stress degradation of the integrated circuit.
摘要翻译：用于检测半导体集成电路的应力退化的监视系统具有放大器电路和劣化测试晶体管。提供了具有耦合到劣化测试晶体管的相应电极的输出的多路复用器。每个多路复用器具有耦合到监视器节点之一和放大器电路的相应节点的输入。在操作中，多路复用器选择性地将降解测试晶体管插入到集成电路或放大器电路中，使得当插入到集成电路中时，劣化测试晶体管在集成电路中遭受应力劣化电压。当降解测试晶体管插入到放大器电路中时，产生指示集成电路的应力劣化的输出信号。

4. 发明申请

US20140191777A1 MONITORING SYSTEM FOR DETECTING DEGRADATION OF INTEGRATED CIRCUIT 有权
标题翻译：用于检测集成电路降级的监控系统
公开(公告)号：US20140191777A1
公开(公告)日：2014-07-10
申请号：US14076286
申请日：2013-11-11
申请人： Zhichen Zhang , Chuanzheng Wang , Qilin Zhang
发明人： Zhichen Zhang , Chuanzheng Wang , Qilin Zhang
IPC分类号： G01R31/28
CPC分类号： G01R31/2856 , G01R31/275 , G01R31/2849
摘要： A monitoring system for detecting stress degradation of a semiconductor integrated circuit has an amplifier circuit and degradation test transistors. Multiplexers are provided that have an output coupled to a respective electrode of the degradation test transistor. Each of the multiplexers has an input coupled to one of the monitor nodes and a respective node of the amplifier circuit. In operation, the multiplexers selectively insert the degradation test transistor into either the integrated circuit or the amplifier circuit so that when inserted into the integrated circuit the degradation test transistor is subjected to stress degradation voltages in the integrated circuit. When the degradation test transistor is inserted into the amplifier circuit, an output signal is generated that is indicative of stress degradation of the integrated circuit.
摘要翻译：用于检测半导体集成电路的应力退化的监视系统具有放大器电路和劣化测试晶体管。提供了具有耦合到劣化测试晶体管的相应电极的输出的多路复用器。每个多路复用器具有耦合到监视器节点之一和放大器电路的相应节点的输入。在操作中，多路复用器选择性地将降解测试晶体管插入到集成电路或放大器电路中，使得当插入到集成电路中时，劣化测试晶体管在集成电路中遭受应力劣化电压。当降解测试晶体管插入到放大器电路中时，产生指示集成电路的应力劣化的输出信号。

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