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    • 3. 发明授权
    • Print controller operation verification system
    • 打印控制器操作验证系统
    • US07251046B2
    • 2007-07-31
    • US10340718
    • 2003-01-13
    • Akihito MochizukiYukihiko OgataIsamu OzawaMasami KatoTakeshi Shinomiya
    • Akihito MochizukiYukihiko OgataIsamu OzawaMasami KatoTakeshi Shinomiya
    • G06F15/00G06K1/00
    • H04N1/40
    • In case of developing an image output apparatus including a controller to generate image data and an engine to form an image on a medium based on the image data, in order to verify the image data from the controller in real time, halftone image data before conversion into a PWM signal is converted into a serial signal and output instead of the PWM signal for output to the engine unit if a controller operation verification apparatus is used instead of the engine unit. Thus, multivalued halftone data not including an error due to a conversion process can be sent to the controller operation verification apparatus without adding signal line and driver circuit dedicated for sending the multivalued halftone data, whereby it is possible to improve development efficiency of the image output apparatus by accurate verification of the output image data.
    • 在显影图像输出装置的情况下,包括基于图像数据生成图像数据的控制器和在介质上形成图像的引擎,以便实时地验证来自控制器的图像数据,在转换之前的半色调图像数据 如果使用控制器操作验证装置代替发动机单元,则将PWM信号转换为串行信号并输出​​而不是PWM信号以输出到发动机单元。 因此,由于转换处理而不包括错误的多值半色调数据可以发送到控制器操作验证装置,而不需要添加专用于发送多值半色调数据的信号线和驱动电路,从而可以提高图像输出的显影效率 通过精确验证输出图像数据的装置。
    • 9. 发明授权
    • Data processing apparatus dual-bus data processing with reduced cpu and
memory requirements
    • 双总线数据处理,降低了CPU和内存需求
    • US5412488A
    • 1995-05-02
    • US886874
    • 1992-05-22
    • Yukihiko Ogata
    • Yukihiko Ogata
    • G06F13/28G06F13/40G06F15/173H04L29/10H04N1/00H04N1/21G06F13/00
    • G06F13/4022G06F15/173
    • Disclosed is a data processing apparatus which makes it possible to perform data processing at high speed by efficiently using a plurality of buses with a small number of microprocessors. The apparatus may be realized in the form of a facsimile apparatus including: a first bus connected to a microprocessor; a second bus which is not connected to the microprocessor; a memory connected to both the first and second buses; a memory control section which mediates between memory accesses from these buses so as to allow each of them to use the memory; a group of circuits for performing data processing through the second bus under the control of the microprocessor; and a DMA controller for effecting high-speed data transfer between each of the circuits and the memory.
    • 公开了一种数据处理装置,其可以通过有效地使用具有少量微处理器的多个总线来高速执行数据处理。 该装置可以以传真装置的形式实现,包括:连接到微处理器的第一总线; 未连接到微处理器的第二总线; 连接到第一和第二总线的存储器; 存储器控制部分,其介于来自这些总线的存储器访问之间,以便它们中的每一个使用存储器; 一组用于在微处理器的控制下通过第二总线进行数据处理的电路; 以及用于在每个电路和存储器之间进行高速数据传输的DMA控制器。