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1. 发明申请

US20110291865A1 METHOD, SYSTEM, AND APPARATUS FOR INTERPOLATING AN OUTPUT OF AN ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：用于插入模拟数字转换器输出的方法，系统和装置
公开(公告)号：US20110291865A1
公开(公告)日：2011-12-01
申请号：US12791694
申请日：2010-06-01
申请人： Han Henry Sun , Kuang-Tsan Wu , Yuejian Wu , Sandy Thomson , John D. McNicol , David J. Krause
发明人： Han Henry Sun , Kuang-Tsan Wu , Yuejian Wu , Sandy Thomson , John D. McNicol , David J. Krause
IPC分类号： H03M7/00
CPC分类号： H03H17/0621 , H03H17/0685 , H03H2017/0298
摘要： A system, method, and apparatus is disclosed for interpolation of an output of an analog to digital converter (ADC) to enable operation of the ADC at a sampling rate that is independent of the sampling rate for a DSP core so as to efficiently enable operation at higher date rates. According to one of the embodiments, an interpolation circuit is coupled between the ADC and DSP core and receives a first plurality of samples of data at the first data rate from the ADC and supplies a plurality of samples of second data at a second data rate to the DSP core; the second data rate being less than the first data rate. According to one of the embodiments, the interpolation circuit includes a memory and a FIR filter circuit having filter tap coefficient values selected to provide attenuation at high frequencies to reduce aliasing noise.
摘要翻译：公开了一种用于对模数转换器（ADC）的输出进行插值的系统，方法和装置，以使得能够以独立于DSP核的采样率的采样速率对ADC进行操作，以便有效地使能操作以较高的日期率。根据实施例之一，内插电路耦合在ADC和DSP内核之间，并从ADC接收第一数据速率的第一多个数据采样，并将第二数据的多个样本以第二数据速率提供给 DSP内核; 第二数据速率小于第一数据速率。根据实施例中的一个，内插电路包括存储器和具有滤波器抽头系数值的FIR滤波器电路，该滤波器抽头系数值被选择以在高频率下提供衰减以减少混叠噪声。

2. 发明授权

US09158356B2 Adaptive voltage scaling based on the results of forward error correction processing 有权
标题翻译：基于前向纠错处理结果的自适应电压缩放
公开(公告)号：US09158356B2
公开(公告)日：2015-10-13
申请号：US13170747
申请日：2011-06-28
申请人： Yuejian Wu , Sandy Thomson , Han Henry Sun
发明人： Yuejian Wu , Sandy Thomson , Han Henry Sun
IPC分类号： G06F11/00 , G06F1/32 , G06F11/07 , G06F11/30
CPC分类号： G06F1/3206 , G06F1/3296 , G06F11/076 , G06F11/3024 , G06F11/3055 , Y02D10/172
摘要： In one implementation, a device may include a voltage regulator circuit, a data processing circuit, and an error correction circuit, where the error correction circuit may correct errors in data processed by the data processing circuit to obtain error-corrected data and output an error-corrected version of the processed data. Additionally, an error monitor circuit may output an error signal indicative of a level of the errors in the processed data. A control circuit may receive the error signal and control the voltage regulator circuit to adjust, based on the error signal, the supply voltage to the data processing circuit. In some implementations, the control circuit may also base its decision to control the voltage regulator circuit based on available timing margins in the data processing circuit.
摘要翻译：在一个实现中，设备可以包括电压调节器电路，数据处理电路和纠错电路，其中纠错电路可以校正由数据处理电路处理的数据中的错误，以获得纠错数据并输出错误 - 已处理数据的已更正版本。此外，错误监视电路可以输出指示处理数据中的错误级别的错误信号。控制电路可以接收误差信号并且控制电压调节器电路基于误差信号来调整数据处理电路的电源电压。在一些实施方案中，控制电路还可以基于其决定，以基于数据处理电路中的可用时序余量来控制电压调节器电路。

3. 发明授权

US08631305B2 Reducing processing bias in a soft forward error correction (FEC) decoder 有权
标题翻译：降低软前向纠错（FEC）解码器中的处理偏差
公开(公告)号：US08631305B2
公开(公告)日：2014-01-14
申请号：US13435823
申请日：2012-03-30
申请人： Stanley H. Blakey , Han Henry Sun , Yuejian Wu
发明人： Stanley H. Blakey , Han Henry Sun , Yuejian Wu
IPC分类号： H03M13/00
CPC分类号： H04B10/00 , H04L1/0045
摘要： A system is configured to receive a word that includes a group of samples; randomly select a subset of the samples; identify first samples, from the subset, with a lowest level of reliability; select another subset of the samples; identify second samples, from the other subset, with a lowest level of reliability; and create a merged subset based on selected first samples and selected second samples. The system is also configured to select a further subset of the samples; identify third samples, from the further subset, with a lowest level of reliability; identify fourth samples, from the merged subset, associated with a lowest level of reliability; create another merged subset based on a greater probability that fourth samples than third samples are included in the other merged subset; and generate another word based a sample from the other merged subset; and process the word using the other word.
摘要翻译：系统被配置为接收包括一组样本的单词; 随机选择样本的一个子集; 从子集中识别具有最低可靠性水平的第一个样本; 选择样品的另一个子集; 从另一个子集中识别具有最低可靠性水平的第二个样本; 并基于所选择的第一样本和所选择的第二样本创建合并的子集。该系统还被配置为选择样本的另一子集; 从另一个子集中确定具有最低可靠性水平的第三个样本; 从合并的子集中确定与最低可靠性相关联的第四个样本; 基于第四个样本比第三个样本包含在另一个合并子集中更大的概率，创建另一个合并子集; 并根据来自其他合并子集的样本生成另一个单词; 并使用其他单词处理单词。

4. 发明申请

US20130259492A1 REDUCING PROCESSING BIAS IN A SOFT FORWARD ERROR CORRECTION (FEC) DECODER 有权
标题翻译：在软前向纠错（FEC）解码器中减少处理偏差
公开(公告)号：US20130259492A1
公开(公告)日：2013-10-03
申请号：US13435823
申请日：2012-03-30
申请人： Stanley H. Blakey , Han Henry Sun , Yuejian Wu
发明人： Stanley H. Blakey , Han Henry Sun , Yuejian Wu
IPC分类号： H04B10/06
CPC分类号： H04B10/00 , H04L1/0045
摘要： A system is configured to receive a word that includes a group of samples; randomly select a subset of the samples; identify first samples, from the subset, with a lowest level of reliability; select another subset of the samples; identify second samples, from the other subset, with a lowest level of reliability; and create a merged subset based on selected first samples and selected second samples. The system is also configured to select a further subset of the samples; identify third samples, from the further subset, with a lowest level of reliability; identify fourth samples, from the merged subset, associated with a lowest level of reliability; create another merged subset based on a greater probability that fourth samples than third samples are included in the other merged subset; and generate another word based a sample from the other merged subset; and process the word using the other word.
摘要翻译：系统被配置为接收包括一组样本的单词; 随机选择样本的一个子集; 从子集中确定具有最低可靠性水平的第一个样本; 选择样品的另一个子集; 从另一个子集中识别具有最低可靠性水平的第二个样本; 并基于所选择的第一样本和所选择的第二样本创建合并的子集。该系统还被配置为选择样本的另一子集; 从另一个子集中确定具有最低可靠性水平的第三个样本; 从合并的子集中确定与最低可靠性相关联的第四个样本; 基于第四个样本比第三个样本包含在另一个合并子集中更大的概率，创建另一个合并子集; 并根据来自其他合并子集的样本生成另一个单词; 并使用其他单词来处理该单词。

5. 发明授权

US08477056B2 Method, system, and apparatus for interpolating an output of an analog-to-digital converter 有权
标题翻译：用于内插模数转换器的输出的方法，系统和装置
公开(公告)号：US08477056B2
公开(公告)日：2013-07-02
申请号：US12791694
申请日：2010-06-01
申请人： Han Henry Sun , Kuang-Tsan Wu , Yuejian Wu , Sandy Thomson , John D. McNicol , David J. Krause
发明人： Han Henry Sun , Kuang-Tsan Wu , Yuejian Wu , Sandy Thomson , John D. McNicol , David J. Krause
IPC分类号： H03M1/12
CPC分类号： H03H17/0621 , H03H17/0685 , H03H2017/0298
摘要： A system, method, and apparatus is disclosed for interpolation of an output of an analog to digital converter (ADC) to enable operation of the ADC at a sampling rate that is independent of the sampling rate for a DSP core so as to efficiently enable operation at higher date rates. According to one of the embodiments, an interpolation circuit is coupled between the ADC and DSP core and receives a first plurality of samples of data at the first data rate from the ADC and supplies a plurality of samples of second data at a second data rate to the DSP core; the second data rate being less than the first data rate. According to one of the embodiments, the interpolation circuit includes a memory and a FIR filter circuit having filter tap coefficient values selected to provide attenuation at high frequencies to reduce aliasing noise.
摘要翻译：公开了一种用于对模数转换器（ADC）的输出进行插值的系统，方法和装置，以使得能够以独立于DSP核的采样率的采样速率对ADC进行操作，以便有效地使能操作以较高的日期率。根据实施例之一，内插电路耦合在ADC和DSP内核之间，并从ADC接收第一数据速率的第一多个数据采样，并将第二数据的多个样本以第二数据速率提供给 DSP内核; 第二数据速率小于第一数据速率。根据实施例中的一个，内插电路包括存储器和具有滤波器抽头系数值的FIR滤波器电路，该滤波器抽头系数值被选择以在高频率下提供衰减以减少混叠噪声。

6. 发明申请

US20130022147A1 COHERENT DETECTION USING COHERENT DECODING AND INTERLEAVING 有权
标题翻译：使用相关解码和交互的相似检测
公开(公告)号：US20130022147A1
公开(公告)日：2013-01-24
申请号：US13250462
申请日：2011-09-30
申请人： Han Henry SUN , Kuang-Tsan WU , Yuejian WU , Sandy THOMSON
发明人： Han Henry SUN , Kuang-Tsan WU , Yuejian WU , Sandy THOMSON
IPC分类号： H04L27/22 , H04B15/00
CPC分类号： H04B10/6165 , H04L1/0041 , H04L1/0045 , H04L1/0071 , H04L1/20 , H04L1/244 , H04L27/223
摘要： A system is configured to receive a block of symbols, associated with a phase-modulated signal that includes data symbols that correspond to a payload associated with the signal, and control symbols; process the control symbols to identify an amount of phase noise associated with the control symbols; reset a phase, associated with each of the data symbols, based on the amount of phase noise and a reference phase; interleave the respective data samples, of each of the data symbols with other data samples, where the interleaved respective data samples cause errors, associated with the respective data samples, to be spread out among the other data samples and reduces an error rate relative to a prior data rate that existed before the interleaving; and perform forward error correction on the interleaved respective data samples.
摘要翻译：系统被配置为接收与包括对应于与所述信号相关联的有效载荷的数据符号的相位调制信号和控制符号相关联的符号块; 处理控制符号以识别与控制符号相关联的相位噪声量; 基于相位噪声量和参考相位复位与每个数据符号相关联的相位; 将每个数据符号的各个数据样本与其他数据样本进行交织，其中交织的相应数据样本导致与各个数据样本相关联的错误，在其他数据样本中展开，并减少相对于在交织之前存在的先前数据速率; 并对交错的各个数据样本执行前向纠错。

7. 发明授权

US06286119B1 Delay fault testing with IEEE 1149.1 有权
标题翻译：延迟故障测试与IEEE 1149.1
公开(公告)号：US06286119B1
公开(公告)日：2001-09-04
申请号：US09218427
申请日：1998-12-22
申请人： Yuejian Wu , Paul P. Soong
发明人： Yuejian Wu , Paul P. Soong
IPC分类号： G01R3128
CPC分类号： G01R31/31858
摘要： An interconnect delay test uses the IEEE 1149.1 standard test access port (TAP) controller. No modification of standard boundary cells is required. Since the standard boundary scan cells are used, circuit board and/or backplane interconnect delay tests do not affect ASIC (application specific integrated circuit) designs. It allows board and system designers to add new interconnect AC tests for any signals at any time without modification of ASICs. Since the method has no impact on the operations of the standard TAP controller, it is possible to use available test softwares for interconnect DC tests to perform the proposed delay test. The method can also be integrated as part of in-system interconnect tests.
摘要翻译：互连延迟测试使用IEEE 1149.1标准测试访问端口（TAP）控制器。不需要对标准边界单元进行修改。由于使用标准边界扫描单元，电路板和/或背板互连延迟测试不影响ASIC（专用集成电路）设计。它允许电路板和系统设计人员随时为任何信号添加新的互连AC测试，而无需修改ASIC。由于该方法对标准TAP控制器的操作没有影响，因此可以使用可用的测试软件进行互连直流测试来执行所提出的延迟测试。该方法也可以作为系统互连测试的一部分进行集成。

8. 发明授权

US08861636B2 Coherent detection using coherent decoding and interleaving 有权
标题翻译：使用相干解码和交织的相干检测
公开(公告)号：US08861636B2
公开(公告)日：2014-10-14
申请号：US13250462
申请日：2011-09-30
申请人： Han Henry Sun , Kuang-Tsan Wu , Yuejian Wu , Sandy Thomson
发明人： Han Henry Sun , Kuang-Tsan Wu , Yuejian Wu , Sandy Thomson
IPC分类号： H04L27/18 , H04L1/20 , H04L1/00 , H04B10/61
CPC分类号： H04B10/6165 , H04L1/0041 , H04L1/0045 , H04L1/0071 , H04L1/20 , H04L1/244 , H04L27/223
摘要： A system is configured to receive a block of symbols, associated with a phase-modulated signal that includes data symbols that correspond to a payload associated with the signal, and control symbols; process the control symbols to identify an amount of phase noise associated with the control symbols; reset a phase, associated with each of the data symbols, based on the amount of phase noise and a reference phase; interleave the respective data samples, of each of the data symbols with other data samples, where the interleaved respective data samples cause errors, associated with the respective data samples, to be spread out among the other data samples and reduces an error rate relative to a prior data rate that existed before the interleaving; and perform forward error correction on the interleaved respective data samples.
摘要翻译：系统被配置为接收与包括对应于与所述信号相关联的有效载荷的数据符号的相位调制信号和控制符号相关联的符号块; 处理控制符号以识别与控制符号相关联的相位噪声量; 基于相位噪声量和参考相位复位与每个数据符号相关联的相位; 将每个数据符号的各个数据样本与其他数据样本进行交织，其中交织的相应数据样本导致与各个数据样本相关联的错误在其它数据样本之间展开，并减少相对于在交织之前存在的先前数据速率; 并对交错的各个数据样本执行前向纠错。

9. 发明申请

US20110182577A1 METHOD, SYSTEM, AND APPARATUS FOR FILTER IMPLEMENTATION USING HERMITIAN CONJUGATES 有权
标题翻译：方法，系统和装置，使用HERMITIAN CONJUGATES进行过滤器实现
公开(公告)号：US20110182577A1
公开(公告)日：2011-07-28
申请号：US12785679
申请日：2010-05-24
申请人： Yuejian Wu
发明人： Yuejian Wu
IPC分类号： H04J14/00
CPC分类号： H04B10/2513
摘要： Filter implementation using Hermitian conjugates and time division multiplexing (TDM) is disclosed to more efficiently compensate for chromatic dispersion of optical signals transmitted over a fiber optic medium. Embodiments for an input, filter, and output sections of a Digital Signal Processor (DSP) are described. The disclosed methods, and corresponding apparatus and systems enables a substantial reduction in the complexity of the hardware needed to implement CD compensation in the DSP. According to another embodiment, Inverse-Fourier transform circuits receive TDM data from the filter section and assemble the TDM data format back to a non-TDM format.
摘要翻译：公开了使用埃米特共轭和时分复用（TDM）的滤波器实现，以更有效地补偿通过光纤介质传输的光信号的色散。描述了数字信号处理器（DSP）的输入，滤波器和输出部分的实施例。所公开的方法和相应的装置和系统能够显着降低在DSP中实现CD补偿所需的硬件的复杂性。根据另一实施例，逆傅立叶变换电路从滤波器部分接收TDM数据，并将TDM数据格式组合成非TDM格式。

10. 发明授权

US06563751B1 System and method for testing TDM sRAMs 有权
标题翻译：用于测试TDM sRAM的系统和方法
公开(公告)号：US06563751B1
公开(公告)日：2003-05-13
申请号：US09749945
申请日：2000-12-29
申请人： Yuejian Wu
发明人： Yuejian Wu
IPC分类号： G11C700
CPC分类号： G11C29/14 , G11C8/16 , G11C11/41
摘要： A technique for testing a static random access memory comprising at least the first port and a second port is disclosed. In one embodiment, the technique may be realized by testing the memory with values through the first port while applying one of a shadow write and a shadow read from the second port and testing the memory through the second port while applying one of the shadow write and the shadow read from the first port. The shadow write may be designed to write specified values into cells of the memory not being tested where the specified values are opposite to values used in testing the memory. The shadow read may be designed to read values from memory that are opposite to the values used in testing the memory.
摘要翻译：公开了一种用于测试包括至少第一端口和第二端口的静态随机存取存储器的技术。在一个实施例中，该技术可以通过在从第二端口施加影子写入和阴影读取中的一个的情况下通过第一端口测试存储器来实现，并且通过第二端口测试存储器，同时施加阴影写入和从第一个港口读取影子。影子写入可能被设计为将指定的值写入未测试的存储器的单元格中，其中指定值与测试存储器中使用的值相反。影子读取可以被设计为从存储器读取与用于测试存储器的值相反的值。

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