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1. 发明授权

US07526050B2 CCK demodulation via symbol decision feedback equalizer 有权
标题翻译：通过符号判决反馈均衡器进行CCK解调
公开(公告)号：US07526050B2
公开(公告)日：2009-04-28
申请号：US10460766
申请日：2003-06-12
申请人： Younggyun Kim , Jaekyun Moon
发明人： Younggyun Kim , Jaekyun Moon
IPC分类号： H03D1/00
CPC分类号： H04B1/71057 , H04B1/7093 , H04B2201/709709 , H04J11/0033 , H04L23/02 , H04L25/03057 , H04L25/03267 , H04L2025/03375 , H04L2025/03503 , H04L2027/0042
摘要： Demodulation techniques for a wireless communication system make use of a decision feedback equalization (DFE) technique to mitigate the effects of multipath channel characteristics on receiver performance. The techniques may be particularly useful in the demodulation of complementary code keying (CCK) symbols. A demodulator that performs such techniques may include a time-variant or time-invariant matched filter, a feedback intersymbol interference (ISI) canceller, a transform unit, a phase rotation estimator and corrector, a pattern-dependent bias canceller, and a maximum picker for symbol decisions. The transform unit may include a bank of correlators, or alternatively a fast Walsh transform unit.
摘要翻译：无线通信系统的解调技术利用判决反馈均衡（DFE）技术来减轻多径信道特性对接收机性能的影响。这些技术在解码补码编码（CCK）符号中可能特别有用。执行这种技术的解调器可以包括时变或时间不变的匹配滤波器，反馈符号间干扰（ISI）消除器，变换单元，相位旋转估计器和校正器，模式相关偏移消除器和最大选择器用于符号决定。变换单元可以包括一组相关器，或者可以包括快速沃尔什变换单元。

2. 发明申请

US20100037119A1 APPARATUS AND METHOD FOR UPDATING CHECK NODE OF LOW-DENSITY PARITY CHECK CODES 审中-公开
标题翻译：检查低密度奇偶校验码代码的装置和方法
公开(公告)号：US20100037119A1
公开(公告)日：2010-02-11
申请号：US12517455
申请日：2007-12-05
申请人： Jong-Ee Oh , Yu-Ro Lee , Chanho Yoon , Minho Cheong , Sok-Kyu Lee , Yoo-Seung Song , Younggyun Kim
发明人： Jong-Ee Oh , Yu-Ro Lee , Chanho Yoon , Minho Cheong , Sok-Kyu Lee , Yoo-Seung Song , Younggyun Kim
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1122 , H03M13/1117 , H03M13/112 , H03M13/6527 , H03M13/6544 , H03M13/6577 , H03M13/658 , H03M13/6583
摘要： An apparatus and method for updating a check node of a low-density parity check (LDPC) code in order to decode the LDPC code are provided. The method includes the operations of: (a) obtaining a first bit of a first minimum value among input values, the number of input values being equal to the number of degrees of the check node, by performing an AND operation on first bits of the input values, the first bits being most significant bits of the input values; (b) obtaining result values by switching and sequentially performing an XOR operation and an OR operation on the first bit of the first minimum value and each of the first bits of the input values; and (c) performing operations (a) and (b) on the result values set as input values and performing operations (a) and (b) a number of times corresponding to the number of bits of each input value, that is, repeating until last bits are set as input values, to thereby obtain the first minimum value, the last bits being least significant bits of the input values. Accordingly, the complexity of hardware is reduced, and super high-speed processing is possible.
摘要翻译：提供了一种用于更新低密度奇偶校验（LDPC）码的校验节点以便解码LDPC码的装置和方法。该方法包括以下操作：（a）通过对所述校验节点的第一比特执行“与”运算，获得输入值中的第一最小值的第一比特，输入值的数目等于校验节点的度数。输入值，第一位是输入值的最高有效位; （b）通过对所述第一最小值的所述第一位和所述输入值的所述第一位中的每一个进行切换和顺序执行异或运算和或运算来获得结果值; 和（c）对设置为输入值的结果值执行操作（a）和（b），并且执行操作（a）和（b）与每个输入值的位数相对应的次数，即重复直到最后的位被设置为输入值为止，从而获得第一最小值，最后的位是输入值的最低有效位。因此，硬件的复杂度降低，超高速处理成为可能。

3. 发明授权

US06728928B2 Modified viterbi detector for jitter noise dominant channels 有权
标题翻译：改进的维特比检测器用于抖动噪声主导通道
公开(公告)号：US06728928B2
公开(公告)日：2004-04-27
申请号：US09681233
申请日：2001-03-02
申请人： Taehyun Jeon , Ming-Tak Leung , Leo Ki-Chun Fu , Younggyun Kim
发明人： Taehyun Jeon , Ming-Tak Leung , Leo Ki-Chun Fu , Younggyun Kim
IPC分类号： H03M1300
CPC分类号： G11B20/10064 , G11B20/10009 , H03M13/41 , H03M13/6331 , H03M13/6343
摘要： A Viterbi detector includes circuitry for receiving an NRZ encoded received signal in an EEPR4 channel to decode the signal according to &lgr;k(i)=(zk−yk(i))2−&agr;(i), wherein &agr;(i) is m &agr;, &agr; is a positive constant, m is a number of transitions within the most current four symbol periods, &lgr;k(i) is a branch metric at time k for an ith Viterbi branch, k is a time period, zk is a received value at time k, &lgr;k(i) is a metric used to determine a next state of the Viterbi based upon a maximum likelihood evaluation for an ith branch, ak, ak−1, ak−2, ak−3 are received state values at respective time periods k, k−1, k−2, and k−3, and yk is an ideal sample associated with an ith branch. The detector is operated to decode a received data value by determining whether the received value is in a space containing first (90) and second (92) possible decode values. The space has a boundary (96) substantially equidistant from the first (90) and second (92) possible decode values and separating the first and second possible decode values. If the received value is within a first portion of the space closest to the first decode value, the received value is decoded as the first decode value. If the received value is within a second portion of the space closest to the second decode value, it is decoded as the second decode value. A value (&agr;) that estimates an amount of jitter noise in a channel (26) through which the received value has passed is produced. The boundary (96) is then moved an additive amount (1&agr;, 2&agr;, 3&agr;) determined by the value that estimates an amount of jitter noise, wherein the boundary is moved (97, 98, 99) to enlarge whichever of the first and second spaces that contains a larger amount of jitter noise.
摘要翻译：维特比检测器包括用于在EEPR4信道中接收NRZ编码的接收信号的电路，用于根据lambdak（i）=（zk-yk（i））2 -al（i）其中α（i）是mα，α是正常数，m是最近四个符号周期内的转换次数，lambdak（i）>是第i个时刻k的分支度量维特比分支，k是时间段，zk是时间k处的接收值，lambdak <（i）>是用于基于第i个分支的最大似然估计来确定维特比的下一个状态的度量， ak，ak-1，ak-2，ak-3在各个时间段k，k-1，k-2和k-3处被接收状态值，yk是与第i个分支相关联的理想样本。通过确定接收到的值是否在包含第一（90）和第二（92）个可能解码值的空间中，检测器被操作来解码所接收的数据值。空间具有与第一（90）和第二（92）可能的解码值基本上等距的边界（96），并且分离第一和第二可能译码值。如果所接收的值在距离第一解码值最近的空间的第一部分内，则接收的值被解码为第一解码值。如果接收的值在距离第二解码值最近的空间的第二部分内，则将其解码为第二解码值。产生估计经过接收值的通道（26）中的抖动噪声量的值（α）。然后，通过估计抖动噪声量确定的添加量（1alpha，2alpha，3alpha）移动边界（96），其中移动边界（97,98,99）以扩大第一和第二包含较大量抖动噪声的空间。

4. 发明授权

US06636120B2 Decimated digital phase-locked loop for high-speed implementation 有权
公开(公告)号：US06636120B2
公开(公告)日：2003-10-21
申请号：US09991680
申请日：2001-11-21
申请人： Bhavesh G. Bhakta , Younggyun Kim
发明人： Bhavesh G. Bhakta , Younggyun Kim
IPC分类号： H03L7093
CPC分类号： G11B20/1025 , G11B20/10037 , G11B20/1403 , H03L7/091 , H03L7/093
摘要： A phase lock loop to control phase error from a first input signal and a second input signal including a phase error detector to detect a phase error signal between the first input signal and the second input signal at a predetermined rate, a down-sampling circuit to down-sample the phase error signal and to output a down-sampled signal at a reduced rate with respect to the predetermined rate, a loop filter to filter the down-sampled signal to obtain a filtered signal, and an up-sampling circuit to up-sample the filtered signal at the predetermined rate.

5. 发明授权

US07610019B2 Apparatus and method for dynamic diversity based upon receiver-side assessment of link quality 有权
标题翻译：基于接收机侧链路质量评估的动态分集装置和方法
公开(公告)号：US07610019B2
公开(公告)日：2009-10-27
申请号：US11449068
申请日：2006-06-08
申请人： Jaekyun Moon , Younggyun Kim , Barrett J. Brickner , Paul C. Edwards , Michael E. Butenhoff
发明人： Jaekyun Moon , Younggyun Kim , Barrett J. Brickner , Paul C. Edwards , Michael E. Butenhoff
IPC分类号： H04B17/00
CPC分类号： H04L1/0001 , H04B7/0811 , H04B7/0814 , H04L1/0015 , H04L1/206
摘要： An apparatus for dynamic diversity signal reception based upon receiver-side link quality assessments includes two or more antennae. At least one switch is connected to the two or more antennae. A dynamic diversity controller is connected to the at least one switch. The dynamic diversity controller includes a link quality assessor to assess link quality and generate a link characterization value. A diversity configuration selector, responsive to the link characterization value, selectively activates the at least one switch to implement a dynamic diversity configuration. The link quality assessor includes a signal strength analyzer, a modem detector, and/or a MAC layer analyzer to assess the received signal and generate the link characterization value.
摘要翻译：基于接收机侧链路质量评估的用于动态分集信号接收的装置包括两个或更多个天线。至少一个开关连接到两个或更多个天线。动态分集控制器连接到至少一个开关。动态分集控制器包括链路质量评估者，以评估链路质量并生成链路特征值。响应于链路特征值的分集配置选择器选择性地激活至少一个交换机以实现动态分集配置。链路质量评估器包括信号强度分析器，调制解调器检测器和/或MAC层分析器，以评估所接收的信号并产生链路表征值。

6. 发明申请

US20070286268A1 Digital phase locked loop 有权
标题翻译：数字锁相环
公开(公告)号：US20070286268A1
公开(公告)日：2007-12-13
申请号：US11894102
申请日：2007-08-20
申请人： Younggyun Kim , Jaekyun Moon
发明人： Younggyun Kim , Jaekyun Moon
IPC分类号： H04B3/46
CPC分类号： H04L27/2662 , H04L25/03159 , H04L27/2657 , H04L27/2676 , H04L2025/03414
摘要： Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. A device corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The device may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.
摘要翻译：在该阶段编码信息的数字通信信号可能容易受到许多来源的相位误差的影响。设备校正载波和采样相位误差以及相位相位噪声。数字锁相环同时跟踪载波相位误差和采样相位误差，并校正频域中的信号。该装置可以使用采样相位误差推进或延迟用于将来自时域的信号转换到频域的采样窗口。

7. 发明授权

US07173990B2 Joint equalization, soft-demapping and phase error correction in wireless system with receive diversity 有权
标题翻译：具有接收分集的无线系统中的联合均衡，软解映射和相位误差校正
公开(公告)号：US07173990B2
公开(公告)日：2007-02-06
申请号：US10141628
申请日：2002-05-06
申请人： Younggyun Kim , Farshid R Rad , Barrett J Brickner , Jaekyun Moon
发明人： Younggyun Kim , Farshid R Rad , Barrett J Brickner , Jaekyun Moon
IPC分类号： H04L1/02 , H04L5/12
CPC分类号： H04B7/0848 , H04B7/0837 , H04L1/06 , H04L25/0204 , H04L25/03159 , H04L25/067 , H04L27/38 , H04L2025/03414 , H04L2025/0342 , H04L2025/03426 , H04L2027/003 , H04L2027/004 , H04L2027/0057
摘要： A wireless communication technique enables equalization, soft demapping and phase error estimation functions to be performed jointly based on multiple observations of a transmitted symbol in wireless communication systems employing receive diversity. Multiple observations of a symbol are obtained from multiple antenna paths in a wireless receiver. Equalization, soft demapping and phase error estimation functions can be integrated within shared hardware, rather than distributed among separate hardware blocks, promoting reduced size, complexity and cost in a wireless receiver.
摘要翻译：无线通信技术使得能够基于采用接收分集的无线通信系统中的传输符号的多个观察来共同执行均衡，软解映射和相位误差估计功能。从无线接收机中的多个天线路径获得符号的多个观察结果。均衡，软解映射和相位误差估计功能可以集成在共享硬件中，而不是分布在不同的硬件块之间，从而在无线接收机中促进尺寸减小，复杂度和成本的降低。

8. 发明授权

US07272175B2 Digital phase locked loop 有权
标题翻译：数字锁相环
公开(公告)号：US07272175B2
公开(公告)日：2007-09-18
申请号：US10137986
申请日：2002-05-01
申请人： Younggyun Kim , Jaekyun Moon
发明人： Younggyun Kim , Jaekyun Moon
IPC分类号： H04L27/14
CPC分类号： H04L27/2662 , H04L25/03159 , H04L27/2657 , H04L27/2676 , H04L2025/03414
摘要： Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. The invention corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The invention may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.
摘要翻译：在该阶段编码信息的数字通信信号可能容易受到许多来源的相位误差的影响。本发明校正载波和采样相位误差以及相位相位噪声。数字锁相环同时跟踪载波相位误差和采样相位误差，并校正频域中的信号。本发明可以使用采样相位误差来推进或延迟用于将来自时域的信号转换到频域的采样窗口。

9. 发明授权

US07146134B2 Apparatus and method for dynamic diversity based upon receiver-side assessment of link quality 有权
公开(公告)号：US07146134B2
公开(公告)日：2006-12-05
申请号：US10117456
申请日：2002-04-04
申请人： Jaekyun Moon , Younggyun Kim , Barrett J Brickner , Paul C Edwards , Michael E Butenhoff
发明人： Jaekyun Moon , Younggyun Kim , Barrett J Brickner , Paul C Edwards , Michael E Butenhoff
IPC分类号： H04B17/00
CPC分类号： H04L1/0001 , H04B7/0811 , H04B7/0814 , H04L1/0015 , H04L1/206
摘要： An apparatus for dynamic diversity signal reception based upon receiver-side link quality assessments includes two or more antennae. At least one switch is connected to the two or more antennae. A dynamic diversity controller is connected to the at least one switch. The dynamic diversity controller includes a link quality assessor to assess link quality and generate a link characterization value. A diversity configuration selector, responsive to the link characterization value, selectively activates the at least one switch to implement a dynamic diversity configuration. The link quality assessor includes a signal strength analyzer, a modem detector, and/or a MAC layer analyzer to assess the received signal and generate the link characterization value.

10. 发明授权

US06738206B2 Decision error compensation technique for decision-directed timing recovery loop 有权
标题翻译：用于决策定时恢复循环的决策误差补偿技术
公开(公告)号：US06738206B2
公开(公告)日：2004-05-18
申请号：US09990962
申请日：2001-11-14
申请人： Younggyun Kim , Bhavesh G. Bhakta , David R. Gruetter
发明人： Younggyun Kim , Bhavesh G. Bhakta , David R. Gruetter
IPC分类号： G11B2020
CPC分类号： G11B20/10009 , G11B21/025 , H03L7/087 , H03L7/091
摘要： A circuit for use in a phase lock loop including a first phase detector to detect a first phase error between input signals, the first phase detector obtaining the first phase error during a first time period, a second phase detector to detect a second phase error between the input signals, the second phase detector obtaining the second phase error during a second time period, the second time period being longer than the first time period, and a compensation circuit to compensate the first phase error with a portion of the second phase error signal.
摘要翻译：一种用于锁相环的电路，包括检测输入信号之间的第一相位误差的第一相位检测器，第一相位检测器在第一时间段期间获得第一相位误差;第二相位检测器，用于检测第一相位误差，所述输入信号，所述第二相位检测器在第二时间段期间获得所述第二相位误差，所述第二时间段长于所述第一时间周期;以及补偿电路，用于补偿所述第一相位误差与所述第二相位误差信号的一部分。

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