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1. 发明授权

US09708706B2 PVD apparatus and method with deposition chamber having multiple targets and magnets 有权
公开(公告)号：US09708706B2
公开(公告)日：2017-07-18
申请号：US13307242
申请日：2011-11-30
申请人： Chung-En Kao , Ming-Chin Tsai , You-Hua Chou , Chen-Chia Chiang , Chih-Tsung Lee , Ming-Shiou Kuo
发明人： Chung-En Kao , Ming-Chin Tsai , You-Hua Chou , Chen-Chia Chiang , Chih-Tsung Lee , Ming-Shiou Kuo
IPC分类号： C23C14/35 , H01J37/34
CPC分类号： C23C14/352 , H01J37/3405 , H01J37/3417
摘要： A thin film deposition system and method provide for multiple target assemblies that may be separately powered. Each target assembly includes a target and associated magnet or set of magnets. The disclosure provides a tunable film profile produced by multiple power sources that separately power the target arrangements. The relative amounts of power supplied to the target arrangements may be customized to provide a desired film and may be varied in time to produce a film with varied characteristics.

2. 发明授权

US09234278B2 CVD conformal vacuum/pumping guiding design 有权
标题翻译： CVD保形真空/抽吸引导设计
公开(公告)号：US09234278B2
公开(公告)日：2016-01-12
申请号：US13354545
申请日：2012-01-20
申请人： You-Hua Chou , Chih-Tsung Lee , Chia-Ho Chen , Chin-Hsiang Lin
发明人： You-Hua Chou , Chih-Tsung Lee , Chia-Ho Chen , Chin-Hsiang Lin
IPC分类号： C23C16/00 , C23C16/44 , C23C16/455
CPC分类号： C23C16/4405 , C23C16/45591
摘要： The present disclosure relates to a guiding element for guiding gas flow within a chamber. The guiding element includes a structure, one or more inlets, an outlet, and a transportation region. The one or more inlets are formed on a first side of the structure. The inlets have inlet sizes selected according to a removal rate and to mitigate gas flow variations within the chamber. The outlet is on a second side of the structure, opposite the first side of the structure. The outlet has an outlet size selected according to the removal rate. The transportation region is within the structure and couples or connects the inlets to the outlet.
摘要翻译：本公开涉及一种用于引导室内的气体流动的引导元件。引导元件包括结构，一个或多个入口，出口和运输区域。一个或多个入口形成在结构的第一侧上。入口具有根据去除速率选择的入口尺寸并减轻腔室内的气体流量变化。出口位于结构的第二侧，与结构的第一侧相对。出口具有根据去除率选择的出口尺寸。运输区域在结构内，并将进口连接或连接到出口。

3. 发明授权

US08742776B2 Mechanisms for resistivity measurement of bump structures 有权
标题翻译：凸块结构电阻率测量机理
公开(公告)号：US08742776B2
公开(公告)日：2014-06-03
申请号：US13012916
申请日：2011-01-25
申请人： You-Hua Chou , Mill-Jer Wang , Pi-Huang Lee , Jeff Wang , Feynmann Chu
发明人： You-Hua Chou , Mill-Jer Wang , Pi-Huang Lee , Jeff Wang , Feynmann Chu
IPC分类号： G01R27/08
CPC分类号： G01R31/048 , H01L22/34 , H01L24/14 , H01L2224/02375 , H01L2224/02381 , H01L2224/0345 , H01L2224/0346 , H01L2224/0347 , H01L2224/0401 , H01L2224/05008 , H01L2224/05019 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05568 , H01L2224/05572 , H01L2224/05655 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/13023 , H01L2224/13083 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/14133 , H01L2224/14515 , H01L2224/16225 , H01L2224/73204 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/04953 , H01L2924/04941 , H01L2924/01014 , H01L2224/13099 , H01L2224/05099 , H01L2924/00 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.
摘要翻译：上述实施例提供了用于凸块电阻率测量的机构。通过在模具的一个或多个角上使用指定的凸块，可以测量凸块的电阻率而不损坏装置并且不需要定制的探测卡。此外，可以在整个晶片上收集隆起电阻率。收集的电阻率数据可用于监测用于形成凸块及其下层的工艺的稳定性和/或健康状况。

4. 发明申请

US20140054653A1 TWO-STEP SHALLOW TRENCH ISOLATION (STI) PROCESS 有权
标题翻译：两步骤快速分离（STI）过程
公开(公告)号：US20140054653A1
公开(公告)日：2014-02-27
申请号：US13594254
申请日：2012-08-24
申请人： Min Hao Hong , You-Hua Chou , Chih-Tsung Lee , Shiu-Ko JangJian , Miao-Cheng Liao , Hsiang-Hsiang Ko , Chen-Ming Huang
发明人： Min Hao Hong , You-Hua Chou , Chih-Tsung Lee , Shiu-Ko JangJian , Miao-Cheng Liao , Hsiang-Hsiang Ko , Chen-Ming Huang
IPC分类号： H01L29/04 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/02538 , H01L21/02609 , H01L21/0334 , H01L21/31053 , H01L21/762 , H01L21/76232 , H01L21/823412 , H01L21/823481 , H01L29/0653 , H01L29/66477 , H01L29/66651 , H01L29/78
摘要： An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.
摘要翻译：集成电路器件和用于制造集成电路器件的工艺。集成电路器件包括其中形成有沟槽的衬底，占据沟槽的隔离材料的第一层，在第一隔离材料层上形成的隔离材料的第二层，衬底上的外延生长的硅层，并且水平相邻第二层隔离材料，以及形成在外延生长的硅上的栅极结构，栅极结构限定沟道。

5. 发明申请

US20130320235A1 UV CURING SYSTEM FOR SEMICONDUCTORS 有权
标题翻译：用于半导体的UV固化系统
公开(公告)号：US20130320235A1
公开(公告)日：2013-12-05
申请号：US13486025
申请日：2012-06-01
申请人： Ming Huei LIEN , Chia-Ho CHEN , Shu-Fen WU , Chih-Tsung LEE , You-Hua CHOU
发明人： Ming Huei LIEN , Chia-Ho CHEN , Shu-Fen WU , Chih-Tsung LEE , You-Hua CHOU
IPC分类号： G21K5/08
CPC分类号： H01L21/6776 , H01L21/3105 , H01L21/67115
摘要： Embodiments of an ultraviolet (UV) curing system for treating a semiconductor substrate such as a wafer are disclosed. The curing system generally includes a processing chamber, a wafer support for holding a wafer in the chamber, a UV radiation source disposed above the chamber, and a UV transparent window interspersed between the radiation source and wafer support. In one embodiment, the wafer support is provided by a belt conveyor operable to transport wafers through the chamber during UV curing. In another embodiment, the UV radiation source is a movable lamp unit that travels across the top of the chamber for irradiating the wafer. In another embodiment, the UV transparent window includes a UV radiation modifier that reduces the intensity of UV radiation on portions of the wafer positioned below the modifier. Various embodiments enhance wafer curing uniformity by normalizing UV intensity levels on the wafer.
摘要翻译：公开了用于处理诸如晶片的半导体衬底的紫外（UV）固化系统的实施例。固化系统通常包括处理室，用于在室中保持晶片的晶片支撑件，设置在室上方的UV辐射源，以及散布在辐射源和晶片支撑件之间的UV透明窗口。在一个实施例中，晶片支撑件由带式输送机提供，其可操作以在UV固化期间将晶片传送通过室。在另一个实施例中，UV辐射源是可移动的灯单元，其移动穿过室的顶部以照射晶片。在另一个实施方案中，UV透明窗口包括UV辐射调节剂，其降低位于调节剂下方的晶片部分上的UV辐射强度。各种实施例通过使晶片上的UV强度水平归一化来增强晶片固化均匀性。

6. 发明申请

US20130239889A1 VALVE PURGE ASSEMBLY FOR SEMICONDUCTOR MANUFACTURING TOOLS 审中-公开
标题翻译：用于半导体制造工具的阀门组件
公开(公告)号：US20130239889A1
公开(公告)日：2013-09-19
申请号：US13419835
申请日：2012-03-14
申请人： Ming Huei LIEN , Chia-Ho CHEN , Shu-Fen WU , Chih-Tsung LEE , You-Hua CHOU
发明人： Ming Huei LIEN , Chia-Ho CHEN , Shu-Fen WU , Chih-Tsung LEE , You-Hua CHOU
IPC分类号： C23C16/00 , F24F7/00
CPC分类号： C23C16/54 , C23C16/4405 , C23C16/4408 , H01L21/67126
摘要： A semiconductor manufacturing tool and method for operating the tool are provided. The semiconductor manufacturing tool includes a process chamber in which plasma operations or ion etching operations are carried out and a valve assembly for opening and closing a valve that provides for loading and unloading substrates into and out of, the semiconductor manufacturing tool. While a processing operation is being carried out in the chamber, a valve assembly purge operation also takes place. The valve assembly purge operation involves inert gases being directed to the valve assembly area to prevent the buildup of particles and contaminating films in the valve assembly. Because the valve assembly is maintained in a clean condition, particle contamination is reduced or eliminated.
摘要翻译：提供了一种用于操作该工具的半导体制造工具和方法。半导体制造工具包括其中执行等离子体操作或离子蚀刻操作的处理室和用于打开和关闭提供用于将衬底加载和卸载到半导体制造工具中的阀的阀组件。当在腔室中进行处理操作时，也发生阀组件清洗操作。阀组件清洗操作涉及惰性气体被引导到阀组件区域，以防止阀组件中的颗粒和污染膜的积聚。因为阀组件保持在清洁状态，颗粒污染被减少或消除。

7. 发明授权

US08518818B2 Reverse damascene process 有权
标题翻译：反向镶嵌工艺
公开(公告)号：US08518818B2
公开(公告)日：2013-08-27
申请号：US13234299
申请日：2011-09-16
申请人： You-Hua Chou , Min Hao Hong , Jian-Shin Tsai , Miao-Cheng Liao , Hsiang Hsiang Ko
发明人： You-Hua Chou , Min Hao Hong , Jian-Shin Tsai , Miao-Cheng Liao , Hsiang Hsiang Ko
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/768 , H01L21/76841 , H01L21/76852 , H01L21/76885 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.
摘要翻译：本公开涉及一种形成后端金属化层的方法。通过在由图案化的光致抗蚀剂层限定的区域内的半导体衬底上形成多个独立金属层结构（即，不被电介质材料包围的金属层结构）来执行该方法。扩散阻挡层以使得扩散阻挡层符合金属层结构的顶部和侧面的方式沉积到金属层结构上。在基板的表面上形成电介质材料以填充金属层结构之间的区域。将衬底平坦化以除去多余的金属和电介质材料并露出金属层结构的顶部。

8. 发明授权

US08497183B2 Devices having a cavity structure and related methods 有权
标题翻译：具有腔结构和相关方法的器件
公开(公告)号：US08497183B2
公开(公告)日：2013-07-30
申请号：US12662681
申请日：2010-04-28
申请人： You-Hua Chou , Hsiang Hsiang Ko , Hung Jui Chang , Yi Ming Chen , Hsien-Wei Lin
发明人： You-Hua Chou , Hsiang Hsiang Ko , Hung Jui Chang , Yi Ming Chen , Hsien-Wei Lin
IPC分类号： H01L21/76
CPC分类号： H01M8/1097 , H01M2008/1095 , Y02P70/56
摘要： A method of making a device. The method comprises providing a first layer including a first material on a surface of a substrate, removing a portion of the first layer and a corresponding portion of the substrate to form an opening in the first layer and a recessed portion in the surface of the substrate, and supplying a liquid mixture to the opening and the recessed portion. The liquid mixture includes a first component having a first chemical affinity to the first material and a second component having a second chemical affinity to the first material, which is smaller than the first chemical affinity. The method also includes removing the second component and forming a second layer including the first component. The second layer covers the recessed portion and adheres to an edge portion of the first layer, such that the second layer and the recessed portion define a cavity.
摘要翻译：制造装置的方法。该方法包括在衬底的表面上提供包括第一材料的第一层，去除第一层的一部分和衬底的对应部分以在第一层中形成开口，并且在衬底的表面中形成凹陷部分并且将液体混合物供应到开口和凹部。液体混合物包括对第一材料具有第一化学亲和力的第一组分和对第一材料具有第二化学亲和力的第二组分，其小于第一化学亲和力。该方法还包括移除第二部件并形成包括第一部件的第二层。第二层覆盖凹部并粘附到第一层的边缘部分，使得第二层和凹部限定一个空腔。

9. 发明申请

US20130189851A1 CVD Conformal Vacuum/Pumping Guiding Design 有权
标题翻译： CVD保形真空/泵送导向设计
公开(公告)号：US20130189851A1
公开(公告)日：2013-07-25
申请号：US13354545
申请日：2012-01-20
申请人： You-Hua Chou , Chih-Tsung Lee , Chia-Ho Chen , Chin-Hsiang Lin
发明人： You-Hua Chou , Chih-Tsung Lee , Chia-Ho Chen , Chin-Hsiang Lin
IPC分类号： H01L21/31 , C23C16/50 , B65D35/38 , C23C16/455
CPC分类号： C23C16/4405 , C23C16/45591
摘要： The present disclosure relates to a guiding element for guiding gas flow within a chamber. The guiding element includes a structure, one or more inlets, an outlet, and a transportation region. The one or more inlets are formed on a first side of the structure. The inlets have inlet sizes selected according to a removal rate and to mitigate gas flow variations within the chamber. The outlet is on a second side of the structure, opposite the first side of the structure. The outlet has an outlet size selected according to the removal rate. The transportation region is within the structure and couples or connects the inlets to the outlet.
摘要翻译：本公开涉及一种用于引导室内的气体流动的引导元件。引导元件包括结构，一个或多个入口，出口和运输区域。一个或多个入口形成在结构的第一侧上。入口具有根据去除速率选择的入口尺寸并减轻腔室内的气体流量变化。出口位于结构的第二侧，与结构的第一侧相对。出口具有根据去除率选择的出口尺寸。运输区域在结构内，并将进口连接或连接到出口。

10. 发明申请

US20130149871A1 CHEMICAL VAPOR DEPOSITION FILM PROFILE UNIFORMITY CONTROL 有权
标题翻译：化学蒸气沉积膜型材均匀性控制
公开(公告)号：US20130149871A1
公开(公告)日：2013-06-13
申请号：US13313106
申请日：2011-12-07
申请人： Ming-Shiou Kuo , Chih-Tsung Lee , You-Hua Chou , Ming-Chin Tsai , Chia-Ho Chen , Chin-Hsiang Lin
发明人： Ming-Shiou Kuo , Chih-Tsung Lee , You-Hua Chou , Ming-Chin Tsai , Chia-Ho Chen , Chin-Hsiang Lin
IPC分类号： H01L21/02 , C23C16/455
CPC分类号： C23C16/44 , C23C16/45565
摘要： The present disclosure provides for methods and systems for controlling profile uniformity of a chemical vapor deposition (CVD) film. A method includes depositing a first layer on a substrate by CVD with a first shower head, the first layer having a first profile, and depositing a second layer over the first layer by CVD with a second shower head, the second layer having a second profile. The combined first layer and second layer have a third profile, and the first profile, the second profile, and the third profile are different from one another.
摘要翻译：本公开提供了用于控制化学气相沉积（CVD）膜的轮廓均匀性的方法和系统。一种方法包括通过CVD用第一喷淋头沉积第一层在CVD衬底上，第一层具有第一轮廓，并且通过CVD与第二喷淋头在第一层上沉积第二层，第二层具有第二轮廓。组合的第一层和第二层具有第三轮廓，并且第一轮廓，第二轮廓和第三轮廓彼此不同。

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