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1. 发明授权

US07579865B1 Selective loading of configuration data into configuration memory cells 有权
标题翻译：将配置数据选择性地加载到配置存储单元中
公开(公告)号：US07579865B1
公开(公告)日：2009-08-25
申请号：US12186027
申请日：2008-08-05
申请人： David L. Rutledge , Wei Han , Yoshita Yerramilli
发明人： David L. Rutledge , Wei Han , Yoshita Yerramilli
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , H03K19/17764
摘要： In one embodiment, a programmable logic device (PLD) such as a field programmable gate array (FPGA) includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data. A plurality of configuration memory cells within the PLD is adapted to receive configuration data transferred from the non-volatile memory. The PLD further includes control logic adapted to determine based on the logic states of the first and second bits stored in the non-volatile memory and prior to any transfer of the configuration data whether to transfer the configuration data from the non-volatile memory to the configuration memory cells.
摘要翻译：在一个实施例中，诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）包括适于存储第一位，第二位和多个配置数据的非易失性存储器。 PLD内的多个配置存储器单元适于接收从非易失性存储器传送的配置数据。 PLD还包括控制逻辑，其适于基于存储在非易失性存储器中的第一和第二位的逻辑状态确定并且在配置数据的任何传送之前是否将配置数据从非易失性存储器传送到配置存储单元。

2. 发明授权

US07944765B1 Programmable logic device with built in self test 有权
标题翻译：可编程逻辑器件内置自检
公开(公告)号：US07944765B1
公开(公告)日：2011-05-17
申请号：US12626289
申请日：2009-11-25
申请人： Wei Han , Yoshita Yerramilli , Loren McLaury , Warren Juenemann
发明人： Wei Han , Yoshita Yerramilli , Loren McLaury , Warren Juenemann
IPC分类号： G11C29/00
CPC分类号： G11C29/08 , G01R31/318519 , G11C2029/0401
摘要： In one embodiment of the invention, an integrated circuit such as a programmable logic device includes volatile memory, nonvolatile memory, and a data shift register for reading data from the nonvolatile memory and for reading data from and writing data to the volatile memory. A built in self test (BIST) circuit is operable to test the nonvolatile memory without the data shift register reading data from the nonvolatile memory. The BIST circuit may include a finite state machine for performing at least one of the following tests on the nonvolatile memory: bulk erase, bulk program; margin bulk program; and/or margin bulk erase. A memory controller responsive to the finite state machine is operable to write data to and read data from the nonvolatile memory during testing of the nonvolatile memory.
摘要翻译：在本发明的一个实施例中，诸如可编程逻辑器件的集成电路包括易失性存储器，非易失性存储器和用于从非易失性存储器读取数据并用于从易失性存储器读取数据并将数据写入到易失性存储器的数据移位寄存器。内置自检（BIST）电路可用于测试非易失性存储器，而数据移位寄存器从非易失性存储器读取数据。 BIST电路可以包括用于对非易失性存储器执行以下测试中的至少一个的有限状态机：批量擦除，批量程序; 保证金批发方案; 和/或边缘批量擦除。响应于有限状态机的存储器控制器可用于在非易失性存储器的测试期间将数据写入非易失性存储器并从其读取数据。

3. 发明授权

US07623378B1 Selective programming of non-volatile memory facilitated by security fuses 有权
标题翻译：通过安全保险丝促进非易失性存储器的选择性编程
公开(公告)号：US07623378B1
公开(公告)日：2009-11-24
申请号：US11416881
申请日：2006-05-02
申请人： Mose Wahlstrom , Wei Han , Yoshita Yerramilli
发明人： Mose Wahlstrom , Wei Han , Yoshita Yerramilli
IPC分类号： G11C11/04
CPC分类号： H03K19/1776 , G11C16/22 , G11C2216/26 , H03K19/17768
摘要： Methods and devices are disclosed herein to provide improved techniques for securing configuration data stored in non-volatile memories of programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a non-volatile memory adapted to store a plurality of configuration data. A plurality of security fuses are adapted to store a plurality of logic states. Control logic is adapted to selectively secure the configuration data within the non-volatile memory based on the logic states stored in the plurality of security fuses.
摘要翻译：本文公开的方法和装置提供用于保护存储在可编程逻辑器件的非易失性存储器中的配置数据的改进技术。例如，根据本发明的实施例，可编程逻辑器件包括适于存储多个配置数据的非易失性存储器。多个安全保险丝适于存储多个逻辑状态。控制逻辑适于基于存储在多个安全保险丝中的逻辑状态来选择性地将配置数据保护在非易失性存储器内。

4. 发明申请

US20080019504A1 Key Generation For Advanced Encryption Standard (AES) Decryption And The Like 有权
标题翻译：高级加密标准（AES）解密等等的密钥生成
公开(公告)号：US20080019504A1
公开(公告)日：2008-01-24
申请号：US11425273
申请日：2006-06-20
申请人： Wei Han , Yoshita Yerramilli
发明人： Wei Han , Yoshita Yerramilli
IPC分类号： H04L9/28
CPC分类号： H04L9/0631 , H04L2209/125
摘要： An apparatus for generating round-key words in accordance with a Rijndael algorithm. In one embodiment of the invention, the apparatus includes (a) a key expansion register block, having a key expansion register adapted to receive a final cipher key of a key expansion schedule in accordance with the Rijndael algorithm; (b) a round constant generator; (c) a first XOR adder adapted to add a first word of the key expansion register to a second word to generate and provide a first sum to the key expansion register block; (d) a transformation block adapted to generate a transformed word based on the first sum and the current round constant over four counts of a first cyclical counter; and (e) a second XOR adder adapted to add the transformed word to the first word of the key expansion register to generate and provide a second sum to the key expansion register block.
摘要翻译：一种用于根据Rijndael算法生成圆键字的装置。在本发明的一个实施例中，该装置包括（a）密钥扩展寄存器块，其具有密钥扩展寄存器，该密钥扩展寄存器适于根据Rijndael算法接收密钥扩展调度的最终密码密钥; （b）圆形恒定发电机; （c）第一XOR加法器，其适于将密钥扩展寄存器的第一字添加到第二字以产生并向密钥扩展寄存器块提供第一和; （d）适于根据第一周期计数器的四个计数基于第一和和当前循环常数生成变换字的变换块; 以及（e）第二XOR加法器，其适用于将所述变换的字添加到所述密钥扩展寄存器的第一个字，以产生并向所述密钥扩展寄存器块提供第二和。

5. 发明授权

US07702100B2 Key generation for advanced encryption standard (AES) Decryption and the like 有权
标题翻译：高级加密标准（AES）的密钥生成解密等
公开(公告)号：US07702100B2
公开(公告)日：2010-04-20
申请号：US11425273
申请日：2006-06-20
申请人： Wei Han , Yoshita Yerramilli
发明人： Wei Han , Yoshita Yerramilli
IPC分类号： H04L9/28 , H04L9/06
CPC分类号： H04L9/0631 , H04L2209/125
摘要： An apparatus for generating round-key words in accordance with a Rijndael algorithm. In one embodiment of the invention, the apparatus includes (a) a key expansion register block, having a key expansion register adapted to receive a final cipher key of a key expansion schedule in accordance with the Rijndael algorithm; (b) a round constant generator; (c) a first XOR adder adapted to add a first word of the key expansion register to a second word to generate and provide a first sum to the key expansion register block; (d) a transformation block adapted to generate a transformed word based on the first sum and the current round constant over four counts of a first cyclical counter; and (e) a second XOR adder adapted to add the transformed word to the first word of the key expansion register to generate and provide a second sum to the key expansion register block.
摘要翻译：一种用于根据Rijndael算法生成圆键字的装置。在本发明的一个实施例中，该装置包括（a）密钥扩展寄存器块，其具有密钥扩展寄存器，该密钥扩展寄存器适于根据Rijndael算法接收密钥扩展调度的最终密码密钥; （b）圆形恒定发电机; （c）第一XOR加法器，其适于将密钥扩展寄存器的第一字添加到第二字以产生并向密钥扩展寄存器块提供第一和; （d）适于根据第一周期计数器的四个计数基于第一和和当前循环常数生成变换字的变换块; 以及（e）第二XOR加法器，其适用于将所述变换的字添加到所述密钥扩展寄存器的第一个字，以产生并向所述密钥扩展寄存器块提供第二和。

6. 发明授权

US07630259B1 Programmable logic device with built in self test 有权
标题翻译：可编程逻辑器件内置自检
公开(公告)号：US07630259B1
公开(公告)日：2009-12-08
申请号：US11959329
申请日：2007-12-18
申请人： Wei Han , Yoshita Yerramilli , Loren McLaury , Warren Juenemann
发明人： Wei Han , Yoshita Yerramilli , Loren McLaury , Warren Juenemann
IPC分类号： G11C29/00
CPC分类号： G11C29/08 , G01R31/318519 , G11C2029/0401
摘要： Various techniques are described to test memory arrays of a programmable logic device (PLD). In one example, a PLD includes a first memory array. The PLD also includes a plurality of sense amplifiers adapted to read a plurality of data values stored by the first memory array and provide a plurality of data signals corresponding to the data values. The PLD further includes a test circuit adapted to test the first memory array. The test circuit is coupled with the sense amplifiers and adapted to compare the data signals with a test signal to provide a pass/fail signal. In addition, the PLD includes a second memory array. The PLD also includes a data shift register adapted to test the second memory array.
摘要翻译：描述了各种技术来测试可编程逻辑器件（PLD）的存储器阵列。在一个示例中，PLD包括第一存储器阵列。 PLD还包括多个读出放大器，用于读取由第一存储器阵列存储的多个数据值，并提供对应于数据值的多个数据信号。 PLD还包括适于测试第一存储器阵列的测试电路。测试电路与读出放大器耦合，并且适于将数据信号与测试信号进行比较以提供通过/失败信号。此外，PLD包括第二存储器阵列。 PLD还包括适于测试第二存储器阵列的数据移位寄存器。

7. 发明授权

US07411417B1 Selective loading of configuration data into configuration memory cells 有权
标题翻译：将配置数据选择性地加载到配置存储单元中
公开(公告)号：US07411417B1
公开(公告)日：2008-08-12
申请号：US11442186
申请日：2006-05-26
申请人： David L. Rutledge , Wei Han , Yoshita Yerramilli
发明人： David L. Rutledge , Wei Han , Yoshita Yerramilli
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , H03K19/17764
摘要： Systems and methods are disclosed herein to provide improved techniques for loading of configuration memory cells in integrated circuits, such as programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data; a plurality of configuration memory cells; and control logic adapted to determine based on values of the first and second bits whether to load the configuration data from the non-volatile memory into the configuration memory cells.
摘要翻译：本文公开了系统和方法，以提供用于在诸如可编程逻辑器件的集成电路中加载配置存储器单元的改进技术。例如，根据本发明的实施例，可编程逻辑器件包括适于存储第一位，第二位和多个配置数据的非易失性存储器; 多个配置存储单元; 以及适于基于第一和第二位的值来确定是否将配置数据从非易失性存储器加载到配置存储器单元中的控制逻辑。

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