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    • 1. 发明授权
    • Quadrature demodulation circuit with carrier control loop
    • 具有载波控制回路的正交解调电路
    • US5905405A
    • 1999-05-18
    • US908069
    • 1997-08-11
    • Yoshiro Ishizawa
    • Yoshiro Ishizawa
    • H04L27/38H03K9/00H04L27/06
    • H04L27/3827
    • In a quadrature circuit, when a large frequency variation is detected, the carrier reproduction is conducted by using the carrier reproduction loop having a signal distortion but a small delay, and then, if the reproduced carrier becomes stable at some degree, the carrier reproduction is conducted by using the carrier reproduction loop having a less signal distortion but a large delay. When the number of the errors detected by an error detecting and correcting circuit is larger than a predetermined value, a selector supplies a digital in-phase signal and a digital quadrature signal outputted from A/D converters located before a waveform equalizer, to a carrier phase error detecting circuit which generates a digital phase error signal feedback through a D/A converter to a local carrier oscillator. When the number of errors detected by the error detecting/correcting circuit is not larger than the predetermined value, the selector supplies a digital in-phase demodulated signal and a digital quadrature demodulated signal outputted from the waveform equalizer to the carrier phase error detecting circuit.
    • 在正交电路中,当检测到大的频率变化时,通过使用具有信号失真但是具有小的延迟的载波再现环路来进行载波再现,然后如果再现的载波在某种程度上变得稳定,则载波再现是 通过使用信号失真较小但延迟大的载波再生环路进行。 当由错误检测和校正电路检测到的错误数量大于预定值时,选择器将位于波形均衡器之前的A / D转换器输出的数字同相信号和数字正交信号提供给载波 相位误差检测电路,通过D / A转换器产生数字相位误差信号反馈到本地载波振荡器。 当由错误检测/校正电路检测到的错误数不大于预定值时,选择器将从波形均衡器输出的数字同相解调信号和数字正交解调信号提供给载波相位误差检测电路。
    • 2. 发明授权
    • Analog-digital converting circuit having high resolution and low power
consumption
    • 模数转换电路具有高分辨率和低功耗
    • US4926175A
    • 1990-05-15
    • US341563
    • 1989-04-20
    • Yoshiro IshizawaHiroshi Morito
    • Yoshiro IshizawaHiroshi Morito
    • H03M1/12H03M1/00
    • H03M1/18
    • An analog-digital converting circuit comprises an analog amplifying circuit having different amplification factors and an input connected to an analog signal input terminal. A first selector is connected at a corresponding number of inputs to receive the plurality of amplified analog signals, respectively. The first selection circuit outputs one analog signal selected from the received amplified analog signals, to an analog-digital converter. A second selector is connected at its an input to receive a digital signal from the analog-digital converter and has a plurality of outputs for outputting the received digital signal from one sequentially alternatively selected from the plurality of outputs. A coefficient multiplying circuit is connected to the outputs of the second selector, and generates multiplied digital signals obtained by multiplying the outputs of the second selector by different coefficeints. A third selector is connected at its corresponding number of inputs to the plurality of outputs of the coefficient multiplying circuit so as to output, as a digital signal, one selected from the plurality of outputs of the coefficient multiplying circuit. A controller is connected to receive the plurality of outputs of the second selector for monitoring respective levels of the plurality of outputs of the second selector and for supplying a selection signal to the third selector so as to cause to select, from the plurality of outputs of the coefficient multiplying circuit, one multiplied digital signal in correspondence to a level of the analog signal inputted to the analog signal input terminal. y