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1. 发明授权

US09087493B2 Liquid crystal display device and driving method thereof 有权
标题翻译：液晶显示装置及其驱动方法
公开(公告)号：US09087493B2
公开(公告)日：2015-07-21
申请号：US11945669
申请日：2007-11-27
申请人： Yong-Chae Jung , Min-Hwa Kim
发明人： Yong-Chae Jung , Min-Hwa Kim
IPC分类号： G09G3/36 , G09G3/32
CPC分类号： G09G3/3688 , G09G3/3266 , G09G2320/0214
摘要： A liquid crystal display device includes a liquid crystal panel, a gate driver, a data driver, and an initial driving control unit. The liquid crystal panel includes a plurality of liquid crystal cells. Each liquid crystal cell is defined by a gate line, a data line and a thin film transistor. The gate driver controls the thin film transistor connected to the gate line of each liquid crystal cell according to a gate control signal. The data driver outputs a pixel signal to the data line of the each liquid crystal cell according to a data control signal. The data driver includes a switch connected to the data line of the each liquid crystal cell. The initial driving control unit is structured to compare a clock count with a predetermined reference value and operable to alternately generate a first state signal and a second state signal based on the comparison. The unit applies the first state signal to the switch during a masking interval. The pixel signal is not output to the data line during the masking interval.
摘要翻译：液晶显示装置包括液晶面板，栅极驱动器，数据驱动器和初始驱动控制单元。液晶面板包括多个液晶单元。每个液晶单元由栅极线，数据线和薄膜晶体管限定。栅极驱动器根据栅极控制信号控制连接到每个液晶单元的栅极线的薄膜晶体管。数据驱动器根据数据控制信号将像素信号输出到每个液晶单元的数据线。数据驱动器包括连接到每个液晶单元的数据线的开关。初始驱动控制单元被构造为将时钟计数与预定参考值进行比较，并且可操作以基于该比较交替地产生第一状态信号和第二状态信号。在屏蔽间隔期间，该单元将第一状态信号施加到开关。在屏蔽间隔期间，像素信号不输出到数据线。

2. 外观设计

USD725674S1 Display screen or portion thereof with transitional graphical user interface 有权
标题翻译：显示屏幕或其部分具有过渡图形用户界面
公开(公告)号：USD725674S1
公开(公告)日：2015-03-31
申请号：US29421476
申请日：2012-07-31
申请人： Yong-Chae Jung , Jee-Yeun Wang , Hee-Kyung Jeon
设计人： Yong-Chae Jung , Jee-Yeun Wang , Hee-Kyung Jeon

3. 外观设计

USD701520S1 Display screen or portion thereof with graphical user interface 有权
公开(公告)号：USD701520S1
公开(公告)日：2014-03-25
申请号：US29419380
申请日：2012-04-27
申请人： Yong-Chae Jung
设计人： Yong-Chae Jung

4. 发明申请

US20140070300A1 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US20140070300A1
公开(公告)日：2014-03-13
申请号：US13724187
申请日：2012-12-21
申请人： Kyung-Tae Jang , Myoung-Bum Lee , Ji-Youn Seo , Chang-Won Lee , Yong-Chae Jung , Woong-Hee Sohn
发明人： Kyung-Tae Jang , Myoung-Bum Lee , Ji-Youn Seo , Chang-Won Lee , Yong-Chae Jung , Woong-Hee Sohn
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/66666 , H01L29/66833 , H01L29/7926
摘要： A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.
摘要翻译：半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体层在垂直方向。这些部分中的至少一些是相邻的多个通道的相应通道。每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极或填充层图案。

5. 外观设计

USD700911S1 Display screen or portion thereof with graphical user interface 有权
公开(公告)号：USD700911S1
公开(公告)日：2014-03-11
申请号：US29419529
申请日：2012-04-30
申请人： Yong-Chae Jung
设计人： Yong-Chae Jung

6. 发明申请

US20100028604A1 HIERARCHICAL STRUCTURES FOR SUPERHYDROPHOBIC SURFACES AND METHODS OF MAKING 审中-公开
标题翻译：超级表面的分层结构及其制造方法
公开(公告)号：US20100028604A1
公开(公告)日：2010-02-04
申请号：US12234900
申请日：2008-09-22
申请人： Bharat Bhushan , Yong Chae Jung , Michael Nosonovsky
发明人： Bharat Bhushan , Yong Chae Jung , Michael Nosonovsky
IPC分类号： B32B3/26 , B05D5/00
CPC分类号： B32B27/08 , B05D1/60 , B05D5/08 , B05D7/02 , B08B17/06 , B08B17/065 , B32B27/06 , B32B27/283 , B32B27/38 , B32B2307/73 , Y10T428/24355 , Y10T428/24479 , Y10T428/24612 , Y10T428/24802
摘要： Embodiments of a superhydrophobic structure comprise a substrate and a hierarchical surface structure disposed on at least one surface of the substrate, wherein the hierarchical surface structure comprises a microstructure comprising a plurality of microasperities disposed in a spaced geometric pattern on at least one surface of the substrate. The fraction of the surface area of the substrate covered by the microasperities is from between about 0.1 to about 1. The hierarchical structure comprises a nanostructure comprising a plurality of nanoasperities disposed on at least one surface of the microstructure.
摘要翻译：超疏水结构的实施方案包括设置在基材的至少一个表面上的基材和分层表面结构，其中分层表面结构包括微结构，其包含在基材的至少一个表面上以间隔几何图案设置的多个微孔。由微透镜覆盖的衬底的表面积的分数为约0.1至约1.层级结构包括纳米结构，其包括设置在微结构的至少一个表面上的多个纳米级。

7. 发明授权

US08916922B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US08916922B2
公开(公告)日：2014-12-23
申请号：US13724187
申请日：2012-12-21
申请人： Kyung-Tae Jang , Myoung-Bum Lee , Ji-Youn Seo , Chang-Won Lee , Yong-Chae Jung , Woong-Hee Sohn
发明人： Kyung-Tae Jang , Myoung-Bum Lee , Ji-Youn Seo , Chang-Won Lee , Yong-Chae Jung , Woong-Hee Sohn
IPC分类号： H01L29/792 , H01L27/115 , H01L29/66
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/66666 , H01L29/66833 , H01L29/7926
摘要： A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.
摘要翻译：半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体层在垂直方向。这些部分中的至少一些是相邻的多个通道的相应通道。每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极或填充层图案。

8. 发明申请

US20140220750A1 Semiconductor Memory Device and Method of Fabricating the Same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20140220750A1
公开(公告)日：2014-08-07
申请号：US14171056
申请日：2014-02-03
申请人： Woonghee Sohn , Kihyun Yun , Myoungbum Lee , Jeonggil Lee , Tai-Soo Lim , Yong Chae Jung
发明人： Woonghee Sohn , Kihyun Yun , Myoungbum Lee , Jeonggil Lee , Tai-Soo Lim , Yong Chae Jung
IPC分类号： H01L27/115
CPC分类号： H01L27/11556 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Provided are a semiconductor device and a method of fabricating the same. The method may include forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate, forming a channel hole to penetrate the electrode structure, forming a data storage layer on a sidewall of the channel hole, and forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate. The electrode layers may be metal-silicide layers, and the insulating layers and the electrode layers may be formed in an in-situ manner using the same deposition system.
摘要翻译：提供半导体器件及其制造方法。该方法可以包括形成包括绝缘层和交替层叠在基板上的电极层的电极结构，形成穿透电极结构的通道孔，在通道孔的侧壁上形成数据存储层，以及在通孔上形成半导体图案数据存储层的侧壁将被电连接到基板。电极层可以是金属硅化物层，并且可以使用相同的沉积系统以原位方式形成绝缘层和电极层。

9. 外观设计

USD707248S1 Display screen or portion thereof with graphical user interface 有权
公开(公告)号：USD707248S1
公开(公告)日：2014-06-17
申请号：US29421477
申请日：2012-07-31
申请人： Yong-Chae Jung , Hee-Kyung Jeon , Jee-Yeun Wang
设计人： Yong-Chae Jung , Hee-Kyung Jeon , Jee-Yeun Wang

10. 外观设计

USD698801S1 Display screen or portion thereof with a generated image 有权
公开(公告)号：USD698801S1
公开(公告)日：2014-02-04
申请号：US29419531
申请日：2012-04-30
申请人： Yong-Chae Jung
设计人： Yong-Chae Jung

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