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    • 6. 发明授权
    • Method of manufacturing a field effect transistor with improved
isolation between electrode
    • 制造具有改善电极间隔离的场效应晶体管的方法
    • US5597743A
    • 1997-01-28
    • US259149
    • 1994-06-13
    • Kazuhiko OndaYoichi Makino
    • Kazuhiko OndaYoichi Makino
    • H01L21/335H01L21/338H01L21/76H01L29/423H01L29/778H01L29/812H01L21/265H01L21/44
    • H01L29/42316H01L21/7605H01L29/66462H01L29/7783
    • A field effect transistor has (a) a channel layer formed by a non-doped first semiconductor material (b) an electron supply layer formed by a doped second semiconductor material having an electron affinity which is lower than the affinity of the first semiconductor material, and (c) a contact layer formed by a doped third semiconductor material having an electron affinity which is higher than the affinity of the second semiconductor material. These layers are successively formed on a substrate of semi-insulating semiconductor material. Ions are implanted and a surface side portion of the contact layer is removed in a region other than at active portions in order to retain at least a part at a substrate side of the contact layer. By this arrangement, an excellent isolation can be achieved without producing large steps due to the mesa shape. Leakage current is not produced. There is no deterioration of the pinch off characteristic and withstand voltage. Noise characteristics and output efficiencies are excellent. There are no interruptions at electrode forming portions and the yield of fabrication is improved.
    • 场效应晶体管具有(a)由非掺杂的第一半导体材料形成的沟道层(b)由电子亲和力低于第一半导体材料的亲和性的掺杂的第二半导体材料形成的电子供给层, 和(c)由具有比第二半导体材料的亲和性高的电子亲和力的掺杂的第三半导体材料形成的接触层。 这些层依次形成在半绝缘半导体材料的衬底上。 植入离子,并且在除活性部分之外的区域中去除接触层的表面侧部分,以便在接触层的基底侧保留至少一部分。 通过这种布置,可以实现优异的隔离,而不会由于台面形状而产生大的台阶。 泄漏电流不产生。 夹断特性和耐压不会变差。 噪声特性和输出效率非常好。 电极形成部分没有中断,制造成品率提高。
    • 7. 发明授权
    • Method for reversing a chip vertically
    • 垂直倒转芯片的方法
    • US07669317B2
    • 2010-03-02
    • US11464230
    • 2006-08-14
    • Yoichi MakinoAkira Kabeshita
    • Yoichi MakinoAkira Kabeshita
    • H05K3/30
    • H01L21/67144Y10T29/4913Y10T29/49131Y10T29/49133Y10T29/53174Y10T29/53478Y10T156/1702
    • In a chip reversing method for holding and vertically reversing a chip placed by a bonding nozzle, the chip is held on a chip holding unit disposed in a reversing member and is vertically reversed by turning the reversing member downward on an reversal shaft. After the reversed chip was received by a chip receiving unit, this chip receiving unit is lowered to a retracted position to return the reversing member to an original position. In this state, the chip receiving unit is raised to position the chip at a height level L for a chip transferring action. As a result, the reversing member does not protrude to above the height level for the chip transfer thereby to interfere with another mechanism, so that the chip mounting actions can be made efficient.
    • 在用于保持并垂直反转由接合喷嘴放置的芯片的芯片反转方法中,芯片被保持在设置在反转构件中的切屑保持单元上,并且通过在反转轴上向下转动反向构件而垂直反转。 在由芯片接收单元接收到反向芯片之后,该芯片接收单元下降到缩回位置,以将反向构件返回到原始位置。 在这种状态下,芯片接收单元升高以将芯片定位在芯片转移动作的高度L处。 结果,反转构件不突出到用于芯片转移的高度水平以上,从而干扰另一机构,使得可以使芯片安装动作有效。
    • 9. 发明授权
    • Method of forming a gate electrode using an insulating film with an opening pattern
    • 使用具有开口图案的绝缘膜形成栅电极的方法
    • US06235626B1
    • 2001-05-22
    • US09201151
    • 1998-11-30
    • Yoichi MakinoHironobu Miyamoto
    • Yoichi MakinoHironobu Miyamoto
    • H01L214763
    • H01L21/28587H01L21/76804
    • The present invention provides a method of forming a gate recess in an insulating film on a substrate for depositing a gate electrode film being in contact with a part of the substrate and also extending at least within the gate recess. The method comprises the steps of: forming an etching mask pattern with a first opening pattern on the insulating film; carrying out a first anisotropic etching process by use of the etching mask pattern at a first selective ratio of the etching mask pattern to the insulating film, thereby to form a first recessed portion having a bottom which lies at a first level higher than an interface level between the insulating film and the substrate; and carrying out a second anisotropic etching process by use of the etching mask pattern again at a second selective ratio of the etching mask pattern to the insulating film, wherein the second selective ratio is higher than the first selective ratio, thereby to form a gate recess which comprises a second recessed portion both having a bottom which lies at the interface level and having first side walls of a first oblique angle and a third recessed portion both having a bottom united with a top of the second recessed portion and having second side walls of a second oblique angle which is smaller than the first oblique angle.
    • 本发明提供一种在衬底上形成绝缘膜中的栅极凹槽的方法,用于沉积与衬底的一部分接触的栅电极膜,并且至少在栅极凹槽内延伸。 该方法包括以下步骤:在绝缘膜上形成具有第一开口图案的蚀刻掩模图案; 通过使用蚀刻掩模图案以与蚀刻掩模图案相对于绝缘膜的第一选择比进行第一各向异性蚀刻处理,从而形成第一凹陷部分,其具有位于比界面高度高的第一高度 在绝缘膜和基板之间; 并且以与蚀刻掩模图案相对于绝缘膜的第二选择比率再次利用蚀刻掩模图案进行第二各向异性蚀刻处理,其中第二选择比高于第一选择比,从而形成栅极凹部 其包括第二凹部,所述第二凹部具有位于界面水平处的底部,并且具有第一倾斜角的第一侧壁和具有与第二凹部的顶部结合的底部的第三凹部,并且具有第二侧壁 第二斜角小于第一斜角。