会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 7. 发明申请
    • Semiconductor designing apparatus
    • 半导体设计装置
    • US20050097495A1
    • 2005-05-05
    • US10960051
    • 2004-10-08
    • Yasuhiro Ishiyama
    • Yasuhiro Ishiyama
    • G06F17/50G06F9/455H01L21/82
    • G06F17/5068G06F17/5045
    • A semiconductor designing apparatus capable of effectively performing a layout designing operation and capable of developing both a circuit designing operation and a layout designing operation at the same time is provided. When a layout designing operation as to a semiconductor memory circuit and a semiconductor analog circuit is manually carried out in a semi-automatic designing manner, since a layout is produced every function, both an internal arranging operation and an internal wiring operation of structural elements can be omitted; also, since the structural elements can be separated, an internal shape of the structural elements can be easily changed; also, since an attribute of an element is changed, a degree of freedom as to a designing operation can be improved; also, since an instance can be added to an element, an insertion such as a substrate contact which does not depend upon a circuit diagram can be added to an arbitrary portion; and further, since a layout designing operation is commenced before a circuit diagram is determined and thereafter matching of net connections is confirmed, both the circuit designing operation and the layout designing operation can be carried out at the same time, so that a designing time period can be shortened.
    • 提供能够有效地执行布局设计操作并且能够同时开发电路设计操作和布局设计操作的半导体设计设备。 当以半自动设计方式手动执行关于半导体存储器电路和半导体模拟电路的布局设计操作时,由于每个功能都产生布局,所以结构元件的内部布置操作和内部布线操作都可以 被省略 而且,由于可以分离结构元件,所以可以容易地改变结构元件的内部形状。 另外,由于元件的属性改变,所以可以提高设计操作的自由度; 另外,由于可以将元件添加到元件,所以可以将不依赖于电路图的基板接点等插入物添加到任意部分; 此外,由于在确定了电路图之前开始布局设计操作,并且此后确认了网络连接的匹配,所以可以同时执行电路设计操作和布局设计操作,使得设计时间段 可以缩短。
    • 10. 发明申请
    • Semiconductor designing apparatus
    • 半导体设计装置
    • US20060206297A1
    • 2006-09-14
    • US11363950
    • 2006-03-01
    • Yasuhiro Ishiyama
    • Yasuhiro Ishiyama
    • G06F17/50
    • G06F17/5022G06F17/5036
    • There are provided a different part detecting portion for detecting the different part of the result of a simulation, a difference detecting portion for detecting a difference in the result of a simulation, an input different part display portion for displaying any of circuits having different simulation modes which has a difference, a different part display portion for displaying a circuit having a difference in the result of a simulation, a condition display portion for displaying, on a circuit diagram, an option to be used in a simulation, a record managing portion for managing the execution history of the result of a simulation, a condition checking portion for ascertaining whether or not a condition is accurately set in each circuit in the execution of a simulation, and a match checking portion for confirming the non-coincidence of the names and numbers of pins between the simulation modes.
    • 提供了用于检测模拟结果的不同部分的不同部分检测部分,用于检测模拟结果的差异的差分检测部分,用于显示具有不同模拟模式的任何电路的输入不同部分显示部分 其具有差异,用于显示具有模拟结果的差异的电路的不同部分显示部分,用于在电路图上显示用于模拟中的选项的条件显示部分,用于在模拟中使用的记录管理部分 管理模拟结果的执行历史,用于确定在执行仿真中每个电路中是否准确地设置条件的条件检查部分,以及用于确认名称的不一致的匹配检查部分,以及 模拟模式之间的引脚数。