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1. 发明授权

US08041912B2 Memory devices with data protection 有权
标题翻译：具有数据保护功能的内存设备
公开(公告)号：US08041912B2
公开(公告)日：2011-10-18
申请号：US11863254
申请日：2007-09-28
申请人： Yu-Lan Kuo , Chun-Yi Lee , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Yu-Lan Kuo , Chun-Yi Lee , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G06F12/00
CPC分类号： G11C8/20 , G06F21/79 , G11C16/22
摘要： A memory device comprises a memory array, a status register coupled with the memory array, and a security register coupled with the memory array and the status register. The memory array contains a number of memory blocks configured to have independent access control. The status register includes at least one protection bit indicative of a write-protection status of at least one corresponding block of the memory blocks that corresponds to the protection bit. The security register includes at least one register-protection bit. The register-protection bit is programmable to a memory-protection state for preventing a state change of at least the protection bit of the status register. The register-protection bit is configured to remain in the memory-protection state until the resetting of the memory device.
摘要翻译：存储器件包括存储器阵列，与存储器阵列耦合的状态寄存器，以及与存储器阵列和状态寄存器耦合的安全寄存器。存储器阵列包含被配置为具有独立访问控制的多个存储器块。状态寄存器包括至少一个保护位，指示对应于保护位的存储器块的至少一个相应块的写保护状态。安全寄存器包括至少一个寄存器保护位。寄存器保护位可编程为存储器保护状态，以防止至少状态寄存器的保护位的状态改变。寄存器保护位被配置为保持存储器保护状态，直到存储器件的复位。

2. 发明申请

US20080059768A1 Method and Apparatus for Communicating a Bit Per Half Clock Cycle over at Least One Pin of an SPI Bus 审中-公开
标题翻译：一种SPI总线的至少一个引脚，用于每半个时钟周期通信位的方法和装置
公开(公告)号：US20080059768A1
公开(公告)日：2008-03-06
申请号：US11773704
申请日：2007-07-05
申请人： Chun-Hsiung Hung , Yu-Lan Kuo
发明人： Chun-Hsiung Hung , Yu-Lan Kuo
IPC分类号： G06F15/00
CPC分类号： G06F13/4291
摘要： Various embodiments increase the speed of communication over an SPI bus by communicating a bit per half clock cycle over at least one pin of an SPI bus.
摘要翻译：通过在SPI总线的至少一个引脚上传送每半个时钟周期的位，各种实施方案通过SPI总线增加通信速度。

3. 发明申请

US20080005434A1 Method and Apparatus for Communicating Data Over Multiple Pins of A Multi-Mode Bus 审中-公开
标题翻译：用于在多模式总线的多个引脚上通信数据的方法和装置
公开(公告)号：US20080005434A1
公开(公告)日：2008-01-03
申请号：US11748984
申请日：2007-05-15
申请人： Chun-Yi Lee , Kuen-Long Chang , Chun-Hsiung Hung , Yu-Lan Kuo
发明人： Chun-Yi Lee , Kuen-Long Chang , Chun-Hsiung Hung , Yu-Lan Kuo
IPC分类号： G06F13/00
CPC分类号： G06F13/4291
摘要： Various embodiments increase the speed of communication over a multi-mode bus by communicating data over multiple pins in the same direction. The bus includes multiple data communication pins communicating over the bus. The bus includes a chip select pin indicating whether communication is occurring between the integrated circuit and another integrated circuit. The bus includes a clock pin. The bus includes a mode control circuit. In one mode, two of the data communication pins communicate in opposite directions between the integrated circuit and another integrated circuit. In another mode, two of the data communication pins communicate in a same direction between the integrated circuit and another integrated circuit. In some embodiments, the bus follows a Serial Peripheral Interface standard. In various embodiments, data is communicated from the integrated circuit to another integrated circuit, or from another integrated circuit to the integrated circuit.
摘要翻译：各种实施例通过在相同方向上在多个引脚上传送数据来增加多模总线上的通信速度。总线包括通过总线通信的多个数据通信引脚。总线包括芯片选择引脚，指示集成电路和另一集成电路之间是否发生通信。总线包括一个时钟引脚。总线包括模式控制电路。在一种模式中，两个数据通信引脚在集成电路和另一个集成电路之间的相反方向上通信。在另一种模式中，两个数据通信引脚在集成电路和另一个集成电路之间沿相同的方向通信。在一些实施例中，总线遵循串行外设接口标准。在各种实施例中，数据从集成电路传送到另一集成电路，或从另一集成电路传送到集成电路。

4. 发明授权

US08190840B2 Memory devices with data protection 有权
标题翻译：具有数据保护功能的内存设备
公开(公告)号：US08190840B2
公开(公告)日：2012-05-29
申请号：US13155404
申请日：2011-06-08
申请人： Yu-Lan Kuo , Chun-Yi Lee , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Yu-Lan Kuo , Chun-Yi Lee , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C8/20 , G06F21/79 , G11C16/22
摘要： A memory device comprises a memory array, a status register, a status-register write-protect bit and a security register. The memory array contains a number of memory blocks. The status register includes at least one protection bit indicative of a protection status of at least one corresponding block of the memory blocks. The status-register write-protect bit is coupled with the status register for preventing a state change of the at least one protection bit. The security register includes at least one register-protection bit for preventing the state change in one of the at least one protection bit of the status register and the status-register write-protect bit.
摘要翻译：存储器件包括存储器阵列，状态寄存器，状态寄存器写保护位和安全寄存器。存储器阵列包含许多存储器块。状态寄存器包括至少一个指示存储块的至少一个相应块的保护状态的保护位。状态寄存器写保护位与状态寄存器耦合以防止至少一个保护位的状态改变。安全寄存器包括至少一个用于防止状态寄存器的至少一个保护位和状态寄存器写保护位之一的状态改变的寄存器保护位。

5. 发明申请

US20120131227A1 SERIAL PERIPHERAL INTERFACE AND METHOD FOR DATA TRANSMISSION 有权
标题翻译：串行外设接口和数据传输方法
公开(公告)号：US20120131227A1
公开(公告)日：2012-05-24
申请号：US13362801
申请日：2012-01-31
申请人： Yu-Lan Kuo , Chun-Hsiung Hung
发明人： Yu-Lan Kuo , Chun-Hsiung Hung
IPC分类号： G06F13/14
CPC分类号： G06F13/4291 , G06F1/22 , G06F13/385 , G06F13/40 , G06F13/4022 , G06F13/404
摘要： A serial peripheral interface of an integrated circuit including multiple pins is provided. The pins are coupled to the integrated circuit. The integrated circuit receives an instruction through only one of the plurality of pins. The integrated circuit receives an address through the plurality of pins. The integrated circuit sends a read out data through the plurality of pins.
摘要翻译：提供了包括多个引脚的集成电路的串行外设接口。引脚耦合到集成电路。集成电路仅通过多个引脚中的一个来接收指令。集成电路通过多个引脚接收地址。集成电路通过多个引脚发送读出数据。

6. 发明授权

US07788438B2 Multi-input/output serial peripheral interface and method for data transmission 有权
标题翻译：多输入/输出串行外设接口和数据传输方法
公开(公告)号：US07788438B2
公开(公告)日：2010-08-31
申请号：US11896846
申请日：2007-09-06
申请人： Yu-Lan Kuo , Chun-Hsiung Hung
发明人： Yu-Lan Kuo , Chun-Hsiung Hung
IPC分类号： G06F13/14 , G06F3/00 , G06F5/00 , G06F13/00 , G06F13/42
CPC分类号： G06F13/4291 , G06F1/22 , G06F13/385 , G06F13/40 , G06F13/4022 , G06F13/404
摘要： A multi-input/output serial peripheral interface of an integrated circuit includes many pins coupled to the integrated circuit. The integrated circuit receives an instruction under a control of selectively using only a first pin or a combination of the first pin, a second pin, a third pin, and a fourth pin of the multi-input/output serial peripheral interface. The integrated circuit receives an address using the first pin, the second pin, the third pin, and the fourth pin of the multi-input/output serial peripheral interface. The integrated circuit sends a read out data using the first pin, the second pin, the third pin, and the fourth pin of the multi-input/output serial peripheral interface.
摘要翻译：集成电路的多输入/输出串行外围接口包括耦合到集成电路的许多引脚。集成电路在仅选择性地仅使用多输入/输出串行外围接口的第一引脚，第二引脚，第三引脚和第四引脚的第一引脚或其组合的控制下接收指令。集成电路使用多输入/输出串行外设接口的第一引脚，第二引脚，第三引脚和第四引脚接收地址。集成电路使用多输入/输出串行外设接口的第一引脚，第二引脚，第三引脚和第四引脚发送读出数据。

7. 发明申请

US20110238939A1 MEMORY DEVICES WITH DATA PROTECTION 有权
标题翻译：具有数据保护功能的存储器件
公开(公告)号：US20110238939A1
公开(公告)日：2011-09-29
申请号：US13155404
申请日：2011-06-08
申请人： Yu-Lan Kuo , Chun-Yi Lee , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Yu-Lan Kuo , Chun-Yi Lee , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G06F12/14
CPC分类号： G11C8/20 , G06F21/79 , G11C16/22
摘要： A memory device comprises a memory array, a status register, a status-register write-protect bit and a security register. The memory array contains a number of memory blocks. The status register includes at least one protection bit indicative of a protection status of at least one corresponding block of the memory blocks. The status-register write-protect bit is coupled with the status register for preventing a state change of the at least one protection bit. The security register includes at least one register-protection bit for preventing the state change in one of the at least one protection bit of the status register and the status-register write-protect bit.
摘要翻译：存储器件包括存储器阵列，状态寄存器，状态寄存器写保护位和安全寄存器。存储器阵列包含许多存储器块。状态寄存器包括至少一个指示存储块的至少一个相应块的保护状态的保护位。状态寄存器写保护位与状态寄存器耦合以防止至少一个保护位的状态改变。安全寄存器包括至少一个用于防止状态寄存器的至少一个保护位和状态寄存器写保护位之一的状态改变的寄存器保护位。

8. 发明申请

US20080091848A1 Multi-input/output serial peripheral interface and method for data transmission 有权
标题翻译：多输入/输出串行外设接口和数据传输方法
公开(公告)号：US20080091848A1
公开(公告)日：2008-04-17
申请号：US11896846
申请日：2007-09-06
申请人： Yu-Lan Kuo , Chun-Hsiung Hung
发明人： Yu-Lan Kuo , Chun-Hsiung Hung
IPC分类号： G06F3/00
CPC分类号： G06F13/4291 , G06F1/22 , G06F13/385 , G06F13/40 , G06F13/4022 , G06F13/404
摘要： A multi-input/output serial peripheral interface of an integrated circuit includes many pins coupled to the integrated circuit. The integrated circuit receives an instruction under a control of selectively using only a first pin or a combination of the first pin, a second pin, a third pin, and a fourth pin of the multi-input/output serial peripheral interface. The integrated circuit receives an address using the first pin, the second pin, the third pin, and the fourth pin of the multi-input/output serial peripheral interface. The integrated circuit sends a read out data using the first pin, the second pin, the third pin, and the fourth pin of the multi-input/output serial peripheral interface.
摘要翻译：集成电路的多输入/输出串行外围接口包括耦合到集成电路的许多引脚。集成电路在仅选择性地仅使用多输入/输出串行外围接口的第一引脚，第二引脚，第三引脚和第四引脚的第一引脚或其组合的控制下接收指令。集成电路使用多输入/输出串行外设接口的第一引脚，第二引脚，第三引脚和第四引脚接收地址。集成电路使用多输入/输出串行外设接口的第一引脚，第二引脚，第三引脚和第四引脚发送读出数据。

9. 发明授权

US08341324B2 Serial peripheral interface and method for data transmission 有权
标题翻译：串行外设接口和数据传输方法
公开(公告)号：US08341324B2
公开(公告)日：2012-12-25
申请号：US13362801
申请日：2012-01-31
申请人： Yu-Lan Kuo , Chun-Hsiung Hung
发明人： Yu-Lan Kuo , Chun-Hsiung Hung
IPC分类号： G06F13/14 , G06F3/00 , G06F5/00 , G06F13/00 , G06F13/42
CPC分类号： G06F13/4291 , G06F1/22 , G06F13/385 , G06F13/40 , G06F13/4022 , G06F13/404
摘要： A serial peripheral interface of an integrated circuit including multiple pins is provided. The pins are coupled to the integrated circuit. The integrated circuit receives an instruction through only one of the plurality of pins. The integrated circuit receives an address through the plurality of pins. The integrated circuit sends a read out data through the plurality of pins.
摘要翻译：提供了包括多个引脚的集成电路的串行外设接口。引脚耦合到集成电路。集成电路仅通过多个引脚中的一个来接收指令。集成电路通过多个引脚接收地址。集成电路通过多个引脚发送读出数据。

10. 发明申请

US20100299473A1 SERIAL PERIPHERAL INTERFACE AND METHOD FOR DATA TRANSMISSION 有权
标题翻译：串行外设接口和数据传输方法
公开(公告)号：US20100299473A1
公开(公告)日：2010-11-25
申请号：US12851156
申请日：2010-08-05
申请人： Yu-Lan Kuo , Chun-Hsiung Hung
发明人： Yu-Lan Kuo , Chun-Hsiung Hung
IPC分类号： G06F13/14
CPC分类号： G06F13/4291 , G06F1/22 , G06F13/385 , G06F13/40 , G06F13/4022 , G06F13/404
摘要： A serial peripheral interface of an integrated circuit including multiple pins and a clock pin is provided. The pins are coupled to the integrated circuit for transmitting an instruction, an address or a read out data. The clock pin is coupled to the integrated circuit for inputting multiple timing pulses. The plurality of pins transmit the instruction, the address or the read out data at rising edges, falling edges or both edges of the timing pulses.
摘要翻译：提供了包括多个引脚和时钟引脚的集成电路的串行外设接口。引脚耦合到集成电路，用于发送指令，地址或读出数据。时钟引脚耦合到集成电路，用于输入多个定时脉冲。多个引脚在定时脉冲的上升沿，下降沿或两个边缘发送指令，地址或读出数据。

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