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1. 发明授权

US09570196B2 Testing through-silicon-vias 有权
标题翻译：通过硅通孔测试
公开(公告)号：US09570196B2
公开(公告)日：2017-02-14
申请号：US14241407
申请日：2012-08-31
申请人： Thomas Vogelsang , William N. Ng , Frederick A. Ware
发明人： Thomas Vogelsang , William N. Ng , Frederick A. Ware
IPC分类号： G01R31/28 , G11C29/04 , G11C29/02 , H01L21/66 , G11C8/10 , H01L25/065
CPC分类号： G11C29/04 , G01R31/2851 , G11C8/10 , G11C29/025 , H01L22/34 , H01L25/0657 , H01L2224/16146 , H01L2225/06513 , H01L2225/06541 , H01L2924/10253 , H01L2924/1434 , H01L2924/00
摘要： Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TS V to at least one of a test input and a test evaluation circuit.
摘要翻译：实施例通常涉及具有硅通孔（TSV）的集成电路器件。在一个实施例中，集成电路（IC）装置包括TSV的场和地址解码器，其将至少一个TSV可选地耦合到测试输入和测试评估电路中的至少一个。在另一实施例中，一种方法包括从至少一个IC器件中的TSV领域中选择一个或多个TSV，以及将每个选择的TS V耦合到测试输入和测试评估电路中的至少一个。

2. 发明授权

US06453330B1 High-precision bilinear interpolation 有权
标题翻译：高精度双线性插值
公开(公告)号：US06453330B1
公开(公告)日：2002-09-17
申请号：US09449012
申请日：1999-11-24
申请人： James T. Battle , William N. Ng
发明人： James T. Battle , William N. Ng
IPC分类号： G06F1717
CPC分类号： G06F17/175
摘要： A circuit is provided for performing a high-precision bilinear interpolation operation. The circuit includes a first interpolation operator for interpolating two operands representing a pair of texels using a weight high component of a weighting value. The first interpolation operator outputs a first result. A second interpolation operator interpolates the two operands representing the pair of texels using a weight low component of the weighting value. The second interpolation operator outputs a second result. A combination operator, coupled to the first and second interpolation operators, combines the first and second results to form a value of higher precision than that yielded by typical circuit implementations for bilinear interpolation operation.
摘要翻译：提供用于执行高精度双线性插值操作的电路。该电路包括第一内插算子，用于使用加权值的加权高分量内插表示一对纹理的两个操作数。第一个插值运算符输出第一个结果。第二插值运算符使用加权值的权重低分量内插表示该对纹理对的两个操作数。第二插值运算符输出第二结果。耦合到第一和第二插值运算符的组合运算符组合第一和第二结果以形成比用于双线性插值运算的典型电路实现产生的精度更高的精度值。

3. 发明授权

US06650334B1 Optimizing texture tag checking for three-dimensional computer graphics 有权
标题翻译：优化三维计算机图形纹理标签检查
公开(公告)号：US06650334B1
公开(公告)日：2003-11-18
申请号：US09245531
申请日：1999-02-05
申请人： John S. Thomson , William N. Ng
发明人： John S. Thomson , William N. Ng
IPC分类号： G09G500
CPC分类号： G06T15/04 , G06T2200/28
摘要： A circuit for texture tag checking includes a first comparison gate which compares a first dimension field of a tag with a first dimension element for a group of texels associated with a sample point. A second comparison gate compares a second dimension field of the tag with a second dimension element for the group of texels. A logic gate, coupled to each of the first and second comparison gates, is associated with one texel of the group of texels. The logic gate outputs a predetermined signal if the first and second dimension fields of the tag are the same as the first and second dimension elements, respectively.
摘要翻译：用于纹理标签检查的电路包括第一比较门，其将标签的第一维度字段与用于与采样点相关联的一组纹素的第一维度元素进行比较。第二比较门将标签的第二维度字段与纹理组的第二维度元素进行比较。耦合到第一和第二比较门中的每一个的逻辑门与一组纹素的一个纹理相关联。如果标签的第一和第二维度字段分别与第一和第二维度元素相同，则逻辑门输出预定信号。

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