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1. 发明授权

US5510281A Method of fabricating a self-aligned DMOS transistor device using SiC and spacers 失效
标题翻译：使用SiC和间隔物制造自对准DMOS晶体管器件的方法
公开(公告)号：US5510281A
公开(公告)日：1996-04-23
申请号：US406440
申请日：1995-03-20
申请人： Mario Ghezzo , Tat-Sing P. Chow , James W. Kretchmer , Richard J. Saia , William A. Hennessy
发明人： Mario Ghezzo , Tat-Sing P. Chow , James W. Kretchmer , Richard J. Saia , William A. Hennessy
IPC分类号： H01L21/04 , H01L29/24 , H01L29/423 , H01L29/45 , H01L29/78 , H01L21/265
CPC分类号： H01L29/1608 , H01L29/42376 , H01L29/4238 , H01L29/45 , H01L29/66068 , H01L29/7802
摘要： A method for fabricating a semiconductor device includes patterning a refractory dielectric layer over a semiconductor layer of a first conductivity type; conformally depositing a first spacer layer over the patterned refractory dielectric layer and the semiconductor layer; patterning the first spacer layer to leave a first spacer adjacent to an edge of the patterned refractory dielectric layer; implanting ions of a second conductivity type to form a base region in the semiconductor layer; conformally depositing a second spacer layer over the patterned refractory dielectric layer and the semiconductor layer; patterning the second spacer layer to leave a second spacer adjacent to an edge of the first spacer; implanting ions of the first conductivity type to form a source region in the base region; removing the first and second spacers; applying a gate insulator layer over at least a portion of the semiconductor layer; conformally depositing a gate electrode layer over the gate insulator layer and the semiconductor layer; and patterning the gate electrode layer to form a gate electrode portion adjacent to an edge of the patterned refractory dielectric layer. Preferably the step of conformally depositing the gate electrode layer includes depositing an electrically conductive layer having the same thickness as a combined width of the first and second spacers. In one embodiment the semiconductor layer includes silicon carbide, the patterned refractory dielectric layer includes silicon dioxide, the spacers include silicon nitride, and the gate electrode layer includes polysilicon.
摘要翻译：一种用于制造半导体器件的方法包括在第一导电类型的半导体层上图形化难熔电介质层; 在图案化的难熔电介质层和半导体层上共形沉积第一间隔层; 图案化第一间隔层以留下邻近图案化耐火介电层的边缘的第一间隔物; 注入第二导电类型的离子以在半导体层中形成基极区; 在图案化的耐火介电层和半导体层上共形沉积第二间隔层; 图案化第二间隔层以留下与第一间隔物的边缘相邻的第二间隔物; 注入第一导电类型的离子以在基区中形成源区; 去除所述第一和第二间隔件; 在所述半导体层的至少一部分上施加栅极绝缘体层; 在所述栅极绝缘体层和所述半导体层上共形沉积栅电极层; 以及图案化栅极电极层以形成邻近图案化耐火介电层的边缘的栅电极部分。优选地，共形沉积栅极电极层的步骤包括沉积具有与第一和第二间隔物的组合宽度相同的厚度的导电层。在一个实施例中，半导体层包括碳化硅，图案化的难熔电介质层包括二氧化硅，间隔物包括氮化硅，并且栅电极层包括多晶硅。

2. 发明授权

US5544038A Synchronous rectifier package for high-efficiency operation 失效
标题翻译：同步整流封装，高效运行
公开(公告)号：US5544038A
公开(公告)日：1996-08-06
申请号：US948051
申请日：1992-09-21
申请人： Rayette A. Fisher , William A. Hennessy , Herman L. N. Wiegman
发明人： Rayette A. Fisher , William A. Hennessy , Herman L. N. Wiegman
IPC分类号： H01L25/18 , H01L27/06 , H02M7/00 , H02M7/21
CPC分类号： H02M7/003 , H01L25/18 , H01L27/0629 , H01L2224/0603 , H01L2224/48137 , H01L2224/49111 , H01L2924/01322 , H01L2924/12032 , H01L2924/1305 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011
摘要： In a synchronous rectifier package, a Schottky diode is situated in parallel, i.e., with like polarity, with the body diode of a synchronous rectifier. The anode of the Schottky diode is connected directly to the source pad of the synchronous rectifier, and the cathode is directly connected to the drain pad. As a result, the synchronous rectifier package has minimal parasitic inductances and resistances, resulting in a highly efficient synchronous rectifier over a wide range of operating frequencies, even at high frequencies. More precise synchronization of gating signals to each individual cell of the synchronous rectifier is also achieved, further increasing rectification efficiency. The synchronous rectifier package is implemented in either a metallized ceramic structure, or a high-density interconnect structure.
摘要翻译：在同步整流器封装中，肖特基二极管与同步整流器的体二极管并联，即具有相同的极性。肖特基二极管的阳极直接连接到同步整流器的源极焊盘，阴极直接连接到漏极焊盘。因此，同步整流器封装具有最小的寄生电感和电阻，从而在宽范围的工作频率下产生高效率的同步整流器，甚至在高频率下也是如此。门控信号与同步整流器的每个单电池的精确同步也得以实现，从而进一步提高整流效率。同步整流器封装以金属化陶瓷结构或高密度互连结构实现。

3. 发明授权

US5475353A Micromachined electromagnetic switch with fixed on and off positions using three magnets 失效
标题翻译：使用三个磁体的具有固定开和关位置的微加工电磁开关
公开(公告)号：US5475353A
公开(公告)日：1995-12-12
申请号：US315520
申请日：1994-09-30
申请人： Waseem A. Roshen , Mario Ghezzo , Richard J. Saia , William A. Hennessy , Bharat S. Bagepalli
发明人： Waseem A. Roshen , Mario Ghezzo , Richard J. Saia , William A. Hennessy , Bharat S. Bagepalli
IPC分类号： H01H50/00 , H01H51/22
CPC分类号： H01H50/005 , H01H2001/0084 , H01H2050/007
摘要： A micromachined electromagnetic switch, including two soft magnets situated in fixed positions above and below a permanent magnet, toggles between two fixed positions by the application of current in an actuator coil for a brief period. The permanent magnet is attached to a micromachined hinge or spring which moves under the action of a net force, thereby opening or closing the switch. Current in the actuator coil changes the relative strength of the magnetic forces due to the soft magnets. In the absence of current in the actuator coil, the switch is kept in the open or closed position by the attractive magnetic force between the permanent magnet and either the upper or lower soft magnet, whereby the stronger force is exercised between the permanent magnet and the nearest soft magnet.
摘要翻译：位于永磁体上下固定位置的两个软磁体的微加工电磁开关通过在致动器线圈中施加电流短暂地切换在两个固定位置之间。永久磁铁连接在微机械加工的铰链或弹簧上，该铰链或弹簧在净力的作用下移动，从而打开或关闭开关。致动器线圈中的电流改变了由于软磁体引起的磁力的相对强度。在致动器线圈中没有电流的情况下，通过永磁体和上软磁体之间的吸引磁力将开关保持在打开或关闭位置，从而在永磁体和最近的软磁铁。

4. 发明授权

US5352629A Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules 失效
标题翻译：通过焊料模粘合剂附着到多芯片模块的半导体芯片的自对准和平面化的工艺
公开(公告)号：US5352629A
公开(公告)日：1994-10-04
申请号：US6297
申请日：1993-01-19
申请人： Kyung W. Paik , William A. Hennessy , Wolfgang Daum
发明人： Kyung W. Paik , William A. Hennessy , Wolfgang Daum
IPC分类号： H01L21/60 , H01L23/13 , H01L21/52 , H01L21/56 , H01L21/603
CPC分类号： H01L23/13 , H01L24/32 , H01L24/75 , H01L24/83 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/75102 , H01L2224/75315 , H01L2224/75317 , H01L2224/7598 , H01L2224/83101 , H01L2224/8319 , H01L2224/83205 , H01L2224/83209 , H01L2224/83801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/0133 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/15153 , H01L2924/15157 , H01L2924/15165 , H01L2924/15787
摘要： A method for attaching a chip to a substrate includes providing the substrate with an outer layer of an electrical conductor which is not wettable by solder and which has a window exposing an inner layer of electrical conductor that is wettable by solder. A solder preform is placed on the window exposing the inner layer, and the chip is placed on the solder preform. The substrate is then heated so as to melt the solder preform. To achieve planarity, the substrate is be positioned in a pressurizing chamber with a film overlay having higher pressure above the film overlay than underneath the overlay, and heated above the melting point of the solder.
摘要翻译：用于将芯片附接到基板的方法包括为基板提供不被焊料润湿的电导体的外层，并且具有暴露由焊料润湿的电导体的内层的窗口。将焊料预制件放置在暴露内层的窗户上，并将芯片放置在焊料预制件上。然后将衬底加热以熔化焊料预制件。为了实现平面性，基板被定位在加压室中，膜覆盖层具有比覆盖层下方更高的压力，并且在焊料的熔点之上被加热。

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