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1. 发明申请

US20220012297A1 Embedding Based Retrieval for Image Search 有权
公开(公告)号：US20220012297A1
公开(公告)日：2022-01-13
申请号：US17277820
申请日：2020-02-28
申请人： Suddha Kalyan Basu , Wei Fan , Daniel Glasner , Sushrut Suresh Karanjkar , Thomas Richard Strohmann , Shubhang Verma , Manas Ashok Pathak , Wenyuan Yin , Sundeep Tirumalareddy
发明人： Suddha Kalyan Basu , Wei Fan , Daniel Glasner , Sushrut Suresh Karanjkar , Thomas Richard Strohmann , Shubhang Verma , Manas Ashok Pathak , Wenyuan Yin , Sundeep Tirumalareddy
IPC分类号： G06F16/9538 , G06F16/583 , G06F16/587 , G06F16/538 , G06N3/02
摘要： Methods, systems, and apparatus including computer programs encoded on a computer storage medium, for retrieving image search results using embedding neural network models. In one aspect, an image search query is received. A respective pair numeric embedding for each of a plurality of image-landing page pairs is determined. Each pair numeric embedding is a numeric representation in an embedding space. An image search query embedding neural network processes features of the image search query and generates a query numeric embedding. The query numeric embedding is a numeric representation of the image search query in the same embedding space. A subset of the image-landing page pairs having pair numeric embeddings that are closest to the query numeric embedding of the image search query in the embedding space are identified as first candidate image search results.

2. 发明申请

US20160050133A1 THROUGHPUT CHARACTERIZATION 有权
标题翻译：通路特征
公开(公告)号：US20160050133A1
公开(公告)日：2016-02-18
申请号：US14779243
申请日：2014-05-08
申请人： Jagjit SINGH ASHTA , Anatoliy IOFFE , Xavier CARRENO BAUTISTA DE LISBONA , Tommy NIELSEN , Mikael KNUDSEN , Guenter KRENZ , Wei FAN , Jesper NIELSEN , Gert PEDERSEN , Ondrej FRANEK
发明人： Jagjit SINGH ASHTA , Anatoliy IOFFE , Xavier CARRENO BAUTISTA DE LISBONA , Tommy NIELSEN , Mikael KNUDSEN , Guenter KRENZ , Wei FAN , Jesper NIELSEN , Gert PEDERSEN , Ondrej FRANEK
IPC分类号： H04L12/26 , H04W72/08
CPC分类号： H04L43/0888 , H04L1/0002 , H04W52/267 , H04W72/085
摘要： In embodiments, apparatuses, methods, and storage media may be described for characterizing throughput of a user equipment (UE) for transmission this transmitted using a modulation and coding scheme (MCS). Specifically, in embodiments throughput of the UE may be characterized using interpolation of UE throughput for one or more discrete signal strength values.
摘要翻译：在实施例中，可以描述装置，方法和存储介质，以表征用于使用调制和编码方案（MCS）发送的用于传输的用户设备（UE）的吞吐量。具体地，在实施例中，UE的吞吐量可以使用针对一个或多个离散信号强度值的UE吞吐量的插值来表征。

3. 发明授权

US08729390B2 Torsion resistant shielded cable 有权
标题翻译：抗扭抗屏蔽电缆
公开(公告)号：US08729390B2
公开(公告)日：2014-05-20
申请号：US13415071
申请日：2012-03-08
申请人： Suy-Tao Liu , Kuo-Wei Fan
发明人： Suy-Tao Liu , Kuo-Wei Fan
IPC分类号： H01B9/02
CPC分类号： H01B9/028 , H01B7/04
摘要： The present invention provides a torsion resistant shielded cable which includes at least one conductor; an insulating layer covering outside the conductor; a first isolating layer surrounding the insulating layer; and a shielded layer including a number of wires, single wires or strand wires, wound around the first isolating layer in a clockwise and counter-clockwise alternative order along an axial direction of the conductor to prevent the strand wires from breaking while the torsion resistant shielded cable is twisted.
摘要翻译：本发明提供了一种抗扭屏蔽电缆，其包括至少一个导体; 覆盖在导体外部的绝缘层; 围绕绝缘层的第一绝缘层; 以及包括多条电线，单线或股线的屏蔽层，沿着导体的轴向方向以顺时针和逆时针方向顺序缠绕在第一隔离层周围，以防止绞合线断裂，同时抗扭屏蔽电缆扭曲。

4. 发明授权

US08724862B2 Image processing apparatus, image processing method, and non-transitory computer readable storage medium 有权
标题翻译：图像处理装置，图像处理方法和非暂时性计算机可读存储介质
公开(公告)号：US08724862B2
公开(公告)日：2014-05-13
申请号：US13406835
申请日：2012-02-28
申请人： Akihiro Minagawa , Yutaka Katsuyama , Nobuyuki Hara , Yoshinobu Hotta , Wei Fan
发明人： Akihiro Minagawa , Yutaka Katsuyama , Nobuyuki Hara , Yoshinobu Hotta , Wei Fan
IPC分类号： G06K9/00
CPC分类号： G06K9/00375 , G06F3/04883
摘要： An image processing apparatus includes a central-portion extracting unit, a classifying unit and a determining unit. The central-portion extracting unit extracts edges from an image area and extracts a plurality of central portions of areas each of which is sandwiched between the edges. The classifying unit groups the central portions by classifying adjacent central portions that have no edge therebetween into a single group. The determining unit determines an area of finger, the area of finger being surrounded by the central portions classified into a group by the classifying unit and peripheral edges of the central portion, the area of finger being an area where a ratio of a luminance gradient in a short side direction to a luminance gradient in a long side direction is within a predetermined threshold.
摘要翻译：图像处理装置包括中央部分提取单元，分类单元和确定单元。中央部分提取单元从图像区域提取边缘并提取多个中心部分，每个中心部分被夹在边缘之间。分类单元通过将没有边缘的相邻中心部分分成单个组来对中心部分进行分组。确定单元确定手指的区域，手指的区域由分类单元和中心部分的外围边缘分为一组的中央部分包围，手指的区域是其中亮度梯度的比率在长边方向上的亮度梯度的短边方向在预定阈值内。

5. 发明授权

US08610169B2 Electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US08610169B2
公开(公告)日：2013-12-17
申请号：US13476908
申请日：2012-05-21
申请人： Wei-Fan Chen
发明人： Wei-Fan Chen
IPC分类号： H01L29/66
CPC分类号： H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： The invention discloses an ESD protection circuit, comprising a P-type substrate; an N-well formed on the P-type substrate; a P-doped region formed on the N-well, wherein the P-doped region is electrically connected to an input/output terminal of a circuit under protection; a first N-doped region formed on the P-type substrate, the first N-doped region is electrically connected to a first node, and the P-doped region, the N-well, the P-type substrate, and the first N-doped region constitute a silicon controlled rectifier; and a second N-doped region formed on the N-well and electrically connected to a second node, wherein a part of the P-doped region and the second N-doped region constitute a discharging path, and when an ESD event occurs at the input/output terminal, the silicon controlled rectifier and the discharging path bypass electrostatic charges to the first and second nodes respectively.
摘要翻译：本发明公开了一种ESD保护电路，包括P型衬底; 在P型衬底上形成的N阱; 形成在所述N阱上的P掺杂区域，其中所述P掺杂区域电连接到保护电路的输入/输出端子; 形成在P型基板上的第一N掺杂区域，第一N掺杂区域电连接到第一节点，P掺杂区域，N阱，P型衬底和第一N掺杂区域掺杂区域构成可控硅整流器; 以及形成在所述N阱上并电连接到第二节点的第二N掺杂区域，其中所述P掺杂区域和所述第二N掺杂区域的一部分构成放电路径，并且当在所述第二N掺杂区域处发生ESD事件时输入/输出端子，可控硅整流器和放电路径分别将静电电荷分别连接到第一和第二节点。

6. 发明申请

US20130307017A1 ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT 有权
标题翻译：静电放电保护电路
公开(公告)号：US20130307017A1
公开(公告)日：2013-11-21
申请号：US13476908
申请日：2012-05-21
申请人： Wei-Fan Chen
发明人： Wei-Fan Chen
IPC分类号： H01L27/088
CPC分类号： H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： The invention discloses an ESD protection circuit, comprising a P-type substrate; an N-well formed on the P-type substrate; a P-doped region formed on the N-well, wherein the P-doped region is electrically connected to an input/output terminal of a circuit under protection; a first N-doped region formed on the P-type substrate, the first N-doped region is electrically connected to a first node, and the P-doped region, the N-well, the P-type substrate, and the first N-doped region constitute a silicon controlled rectifier; and a second N-doped region formed on the N-well and electrically connected to a second node, wherein a part of the P-doped region and the second N-doped region constitute a discharging path, and when an ESD event occurs at the input/output terminal, the silicon controlled rectifier and the discharging path bypass electrostatic charges to the first and second nodes respectively.
摘要翻译：本发明公开了一种ESD保护电路，包括P型衬底; 在P型衬底上形成的N阱; 形成在所述N阱上的P掺杂区域，其中所述P掺杂区域电连接到保护电路的输入/输出端子; 形成在P型基板上的第一N掺杂区域，第一N掺杂区域电连接到第一节点，P掺杂区域，N阱，P型衬底和第一N掺杂区域掺杂区域构成可控硅整流器; 以及形成在所述N阱上并电连接到第二节点的第二N掺杂区域，其中所述P掺杂区域和所述第二N掺杂区域的一部分构成放电路径，并且当在所述第二N掺杂区域处发生ESD事件时输入/输出端子，可控硅整流器和放电路径分别将静电电荷分别连接到第一和第二节点。

7. 发明授权

US08572107B2 Identifying inconsistencies in object similarities from multiple information sources 有权
标题翻译：识别来自多个信息源的对象相似性的不一致
公开(公告)号：US08572107B2
公开(公告)日：2013-10-29
申请号：US13316178
申请日：2011-12-09
申请人： Wei Fan , Jing Gao , Srinivasan Parthasarathy , Deepak Turaga
发明人： Wei Fan , Jing Gao , Srinivasan Parthasarathy , Deepak Turaga
IPC分类号： G06F17/30
CPC分类号： G06F17/30598 , G11B27/32
摘要： A horizontal anomaly detection method includes receiving at plurality of objects described in a plurality of information sources, wherein each individual information source captures a plurality of similarity relationships between the objects, combining the information sources to determine a similarity matrix whose entries represent quantitative scores of similarity between pairs of the objects, and identifying at least one horizontal anomaly of the objects within the similarity matrix, wherein the horizontal anomalies are anomalous relationships across the plurality of information sources.
摘要翻译：水平异常检测方法包括在多个信息源中描述的多个对象处接收，其中每个单独的信息源捕获对象之间的多个相似关系，组合信息源以确定其条目表示相似度的定量分数的相似性矩阵在所述对象之间，并且识别所述相似性矩阵内的对象的至少一个水平异常，其中所述水平异常是所述多个信息源之间的异常关系。

8. 发明申请

US20130158956A1 SELECTING METHOD OF LIGHT GUIDE PLATE OF BACKLIGHT MODULE 有权
标题翻译：背光模组光导板的选择方法
公开(公告)号：US20130158956A1
公开(公告)日：2013-06-20
申请号：US13380889
申请日：2011-12-15
申请人： Chechang Hu , Kuangyao Chang , Lei Sun , Wei Fan
发明人： Chechang Hu , Kuangyao Chang , Lei Sun , Wei Fan
IPC分类号： G06F17/50
CPC分类号： G02B6/0043 , G02B6/0051 , G02B6/0053 , G02B6/0065 , G02F1/133615
摘要： A selecting method of light guide plate of backlight module is described. The selecting method includes the steps of: calculating a plurality of mura indexes (MI) corresponding to a plurality of mura statuses of a plurality of first light guide plate (LGP) types, respectively; defining a plurality of film structures, wherein each of the film structures corresponds to each of mura indexes for mapping the mura indexes (MI) of the first LGP types with the film structures to construct a mapping database; and selecting one of the film structures and one of the mura indexes (MI) correspondingly from the mapping database for determining a critical dot dimension (CDD) of a second LGP type of the selected film structure. The selecting method avoids the mura, speed up the research and development procedure of the backlight module, labor cost and manufacturing cost when the LGP is assembled with the film structure.
摘要翻译：描述背光模块的导光板的选择方法。所述选择方法包括以下步骤：分别计算与多个第一导光板（LGP）类型的多个mura状态对应的多个mura索引（MI）; 定义多个胶片结构，其中每个胶片结构对应于每个mura索引，用于将第一LGP类型的mura索引（MI）与胶片结构映射以构建映射数据库; 以及从所述映射数据库相应地选择所述胶片结构之一和所述mura索引（MI）中的一个，以确定所选择的胶片结构的第二LGP类型的临界点尺寸（CDD）。选择方法避免了光环，加快了背光模块的研发过程，人造成本和制造成本，当LGP与胶片结构组装时。

9. 发明授权

US08433987B2 Method for high-efficient implementation of de-rate matching including HARQ combining for LTE 有权
标题翻译：用于高效率地实现包括用于LTE的HARQ组合的去速率匹配的方法
公开(公告)号：US08433987B2
公开(公告)日：2013-04-30
申请号：US12869901
申请日：2010-08-27
申请人： Wei Fan , Weifeng Li , Jiajun Zhang
发明人： Wei Fan , Weifeng Li , Jiajun Zhang
IPC分类号： H03M13/03
CPC分类号： H03M13/2957 , H03M13/6306 , H03M13/635 , H03M13/6525 , H04L1/005 , H04L1/0066 , H04L1/0067 , H04L1/0071 , H04L1/1812
摘要： Embodiments of the invention provide a method of de-rate matching without NULL bits skipping. Date is received without NULLs and inputted into a LLR combining block. The history data without NULLs is buffered. Log-likelihood ratio (LLR) combining is called before de-rate matching. The output of LLR combining is de-interleaved. The reading pointer is offset to forge NULLs. Finally, de-interleaving output without NULLs is sent to a turbo decoder.
摘要翻译：本发明的实施例提供了一种在没有NULL位跳过的情况下进行速率匹配的方法。收到没有NULL的日期并输入到LLR组合块。没有NULL的历史数据被缓冲。对数似然比（LLR）组合在去速率匹配之前被称为。 LLR组合的输出被解交织。读取指针被偏移以伪造NULL。最后，没有NULL的解交织输出被发送到turbo解码器。

10. 发明授权

US08390070B2 Electrostatic discharge protection device and electrostatic discharge protection circuit thereof 有权
标题翻译：静电放电保护装置及其静电放电保护电路
公开(公告)号：US08390070B2
公开(公告)日：2013-03-05
申请号：US13080662
申请日：2011-04-06
申请人： Wei-Fan Chen
发明人： Wei-Fan Chen
IPC分类号： H01L29/786
CPC分类号： H01L27/0262 , H01L29/7436 , H01L29/87
摘要： The ESD protection device includes a substrate, a well, a first doped region and a second doped region. The substrate has a first conductive type, and the substrate is electrically connected to a first power node. The well has a second conductive type, and is disposed in the substrate. The first doped region has the first conductive type, and is disposed in the well. The first doped region and the well are electrically connected to a second power node. The second doped region has the second conductive type, and is disposed in the substrate. The second doped region is in a floating state.
摘要翻译： ESD保护器件包括衬底，阱，第一掺杂区和第二掺杂区。衬底具有第一导电类型，并且衬底电连接到第一电力节点。阱具有第二导电类型，并且设置在基板中。第一掺杂区域具有第一导电类型，并且设置在阱中。第一掺杂区域和阱电连接到第二功率节点。第二掺杂区域具有第二导电类型，并且设置在基板中。第二掺杂区域处于浮置状态。

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