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1. 发明授权

US08640010B2 Decoding apparatus and decoding method 失效
标题翻译：解码装置和解码方法
公开(公告)号：US08640010B2
公开(公告)日：2014-01-28
申请号：US12335802
申请日：2008-12-16
申请人： Toshiyuki Miyauchi , Masayuki Hattori , Takashi Yokokawa
发明人： Toshiyuki Miyauchi , Masayuki Hattori , Takashi Yokokawa
IPC分类号： G06F11/00
CPC分类号： H03M13/15 , H03M13/1515 , H03M13/45
摘要： Disclosed herein is a decoding apparatus that performs soft-decision decoding on a linear block code, the apparatus including a hard-decision decoder configured to perform hard-decision decoding on a received word using a hard-decision decoding algorithm; and a soft-decision decoder configured to perform, using a soft-decision algorithm, soft-decision decoding merely on a received word for which the hard-decision decoder has failed in the hard-decision decoding.
摘要翻译：本发明公开了一种对线性块码执行软判决解码的解码装置，该装置包括：硬判决解码器，被配置为使用硬判决解码算法对接收到的字执行硬判决解码; 以及软判决解码器，其被配置为仅在硬判决解码器在硬判决解码中已经失败的接收到的字上执行软判决算法的软判决解码。

2. 发明授权

US08464124B2 Receiving apparatus, receiving method and program, and receiving system 有权
标题翻译：接收装置，接收方法和程序，以及接收系统
公开(公告)号：US08464124B2
公开(公告)日：2013-06-11
申请号：US12783291
申请日：2010-05-19
申请人： Naomichi Kishimoto , Hideyuki Matsumoto , Toshiyuki Miyauchi , Yuichi Mizutani
发明人： Naomichi Kishimoto , Hideyuki Matsumoto , Toshiyuki Miyauchi , Yuichi Mizutani
IPC分类号： H03M13/00
CPC分类号： H03M13/1128 , H03M13/1105 , H03M13/3715 , H03M13/6552 , H04L1/0053 , H04L1/0057
摘要： A receiving apparatus receives a low density parity check (“LCPC”) code and decode the LCPC code to provide for error check capabilities. A bit error rate (“BER”) controlling section is the frequency of the LCPC by using an index comprised of BER conditional information that indicates communication conditions affecting the power consumption at the time of decoding. The frequency is controlled on the basis of a reception interval of the low density parity check code.
摘要翻译：接收装置接收低密度奇偶校验（“LCPC”）码并解码LCPC码以提供错误检查能力。差错率（“BER”）控制部分是通过使用由BER条件信息组成的索引来指示LCPC的频率，该条件信息指示在解码时影响功耗的通信条件。基于低密度奇偶校验码的接收间隔来控制频率。

3. 发明授权

US08451966B2 Information processor and information processing method, display device, and program 有权
标题翻译：信息处理器和信息处理方法，显示设备和程序
公开(公告)号：US08451966B2
公开(公告)日：2013-05-28
申请号：US12567837
申请日：2009-09-28
申请人： Hidetoshi Kawauchi , Toshiyuki Miyauchi , Takashi Yokokawa , Takuya Okamoto , Hiroyuki Kamata
发明人： Hidetoshi Kawauchi , Toshiyuki Miyauchi , Takashi Yokokawa , Takuya Okamoto , Hiroyuki Kamata
IPC分类号： H03D1/06 , H03K5/01 , H03K5/159
CPC分类号： H04L25/0212 , H04L25/022 , H04L25/0232 , H04L27/2647 , H04L27/2665
摘要： Disclosed herein is an information processor, including: a receiving section configured to receive an OFDM signal transmitted in accordance with an OFDM system; a FFT arithmetically operating section configured to carry out FFT for a signal within a predetermined interval of the OFDM signal; a delay profile estimating section configured to estimate delay profiles from the OFDM signal received by the receiving section; an inter-symbol interference amount estimating section configured to estimate inter-symbol interference amounts for a plurality of candidates for the predetermined interval, respectively, by using the delay profiles estimated by the delay profile estimating section; and a searching section configured to search for the candidate having the minimum inter-symbol interference amount estimated by the inter-symbol interference amount estimating section from among the plurality of candidates in the predetermined interval, and supply data on the candidate thus searched for as the predetermined interval to the FFT arithmetically operating section.
摘要翻译：本文公开了一种信息处理器，包括：接收部分，被配置为接收根据OFDM系统传输的OFDM信号; FFT算术运算部，被配置为对所述OFDM信号的预定间隔内的信号进行FFT; 延迟分布估计部，被配置为从所述接收部接收到的OFDM信号估计延迟分布; 符号间干扰量估计部，被配置为通过使用由所述延迟分布估计部估计出的延迟分布，分别估计所述预定间隔的多个候选的符号间干扰量; 以及搜索部，被配置为从所述预定间隔中的所述多个候选中搜索具有由所述符号间干扰量估计部估计的最小符号间干扰量的候选，并且将所搜索的候选者的数据提供为到FFT运算部分的预定间隔。

4. 发明授权

US08238459B2 Decoding device and method, receiving device and method, and program 有权
标题翻译：解码设备和方法，接收设备和方法以及程序
公开(公告)号：US08238459B2
公开(公告)日：2012-08-07
申请号：US12361199
申请日：2009-01-28
申请人： Takashi Yokokawa , Yasuhiro Iida , Toshiyuki Miyauchi , Takashi Hagiwara , Takanori Minamino , Naoya Haneda
发明人： Takashi Yokokawa , Yasuhiro Iida , Toshiyuki Miyauchi , Takashi Hagiwara , Takanori Minamino , Naoya Haneda
IPC分类号： H04L23/02
CPC分类号： H04L27/3827 , H04L1/0054 , H04L1/208 , H04L7/042
摘要： A decoding device that decodes demodulated data obtained by demodulating a quadrature modulated signal arising from digital modulation of a carrier and detects synchronization, the decoding device includes, a decoder configured to decode first demodulated data that is the demodulated data obtained by demodulating the quadrature modulated signal and is composed of in-phase axis data and quadrature axis data. The decoding device decodes second demodulated data obtained by interchanging the in-phase axis data and the quadrature axis data of the first demodulated data. A synchronization detector is configured to detect a boundary between predetermined information symbol sequences from first decoded data obtained by decoding the first demodulated data and detect the boundary from second decoded data obtained by decoding the second demodulated data. The synchronization detector selects and outputs one of the first decoded data and the second decoded data based on a result of the detection of the boundary.
摘要翻译：一种解码装置，对通过解调由载波的数字调制产生的正交调制信号而获得的解调数据进行解码，并检测同步，解码装置包括：解码器，被配置为对作为通过解调正交调制信号而获得的解调数据的第一解调数据进行解码并且由同相轴数据和正交轴数据组成。解码装置对通过交换同相轴数据和第一解调数据的正交轴数据而获得的第二解调数据进行解码。同步检测器被配置为从通过解码第一解调数据获得的第一解码数据检测预定信息符号序列之间的边界，并通过解码第二解调数据获得的第二解码数据检测边界。同步检测器基于边界检测的结果选择并输出第一解码数据和第二解码数据中的一个。

5. 发明授权

US08175204B2 Receiving device, signal processing method, and program 有权
标题翻译：接收设备，信号处理方法和程序
公开(公告)号：US08175204B2
公开(公告)日：2012-05-08
申请号：US12544288
申请日：2009-08-20
申请人： Hidetoshi Kawauchi , Yuken Goto , Takuya Okamoto , Toshiyuki Miyauchi
发明人： Hidetoshi Kawauchi , Yuken Goto , Takuya Okamoto , Toshiyuki Miyauchi
IPC分类号： H04B1/10
CPC分类号： H04L25/0234 , H04L5/0007 , H04L5/0048 , H04L25/0216 , H04L25/022 , H04L25/03159 , H04L27/2605 , H04L27/2647 , H04L27/2657 , H04L27/2662 , H04L2025/03414
摘要： A receiving device includes: a pilot extracting section; a first estimating section; a second estimating section; a third estimating section; a distortion correcting section; and a filter controlling section.
摘要翻译：接收装置包括：导频提取部分; 第一个估计部分; 第二估计部分; 第三估计部分; 失真校正部; 和滤波器控制部。

6. 发明申请

US20100306615A1 Receiving Apparatus, Receiving Method and Program, and Receiving System 有权
标题翻译：接收装置，接收方法和程序以及接收系统
公开(公告)号：US20100306615A1
公开(公告)日：2010-12-02
申请号：US12783120
申请日：2010-05-19
申请人： Naomichi KISHIMOTO , Hideyuki Matsumoto , Toshiyuki Miyauchi , Yuichi Mizutani
发明人： Naomichi KISHIMOTO , Hideyuki Matsumoto , Toshiyuki Miyauchi , Yuichi Mizutani
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/1128 , H03M13/1165 , H03M13/3715 , H03M13/6502
摘要： Disclosed herein is a receiving apparatus, including: a decoding section configured to receive and decode an low density parity check code; and a decoding control section configured to control a frequency of the decoding on the basis of conditional information that is an index indicative of a communication condition that influences power consumption in the decoding section.
摘要翻译：这里公开了一种接收装置，包括：解码部分，被配置为接收和解码低密度奇偶校验码; 以及解码控制部分，被配置为基于作为指示在解码部分中影响功耗的通信条件的索引的条件信息来控制解码的频率。

7. 发明申请

US20080168333A1 DECODING METHOD AND DECODING APPARATUS AS WELL AS PROGRAM 有权
标题翻译：解码方法和解码设备作为程序
公开(公告)号：US20080168333A1
公开(公告)日：2008-07-10
申请号：US11959551
申请日：2007-12-19
申请人： Makiko YAMAMOTO , Satoshi Okada , Toshiyuki Miyauchi , Takashi Yokokawa
发明人： Makiko YAMAMOTO , Satoshi Okada , Toshiyuki Miyauchi , Takashi Yokokawa
IPC分类号： H03M13/00
CPC分类号： H03M13/114 , H03M13/1111 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2936 , H03M13/2948 , H03M13/3905 , H03M13/4146
摘要： A decoding method for sorting received words in the order of the magnitude of the reliability of the received words, performing belief propagation using a parity check matrix diagonalized in the order to update the reliabilities, and repetitively performing the sorting and the belief propagation for the updated values, includes an inner repeated decoding process step of performing belief propagation using a parity check matrix diagonalized in an order of columns corresponding to symbols having comparatively low reliability values of the received words to update the reliability and repetitively performing the belief propagation based on the updated reliability; the inner repeated decoding process step in the second or later cycle of repetition thereof including diagonalization of the parity check matrix for restricted ones of the columns of the parity check matrix.
摘要翻译：一种用于按接收字的可靠性大小的顺序对接收到的字进行分类的解码方法，使用以对等化的奇偶校验矩阵来执行置信传播，以更新可靠性，并且重复地执行用于更新的可更新的排序和置信传播值包括内部重复解码处理步骤，其使用对应于与所接收到的字的具有相对低的可靠性值的符号相对应的列的顺序对角化的奇偶校验矩阵来执行置信传播，以更新可靠性并基于更新后的重新执行置信传播可靠性; 内部重复解码处理步骤在其重复的第二或更晚的循环中，包括奇偶校验矩阵的有限列的奇偶校验矩阵的对角化。

8. 发明申请

US20070104296A1 Viterbi decoding apparatus 有权
标题翻译：维特比解码装置
公开(公告)号：US20070104296A1
公开(公告)日：2007-05-10
申请号：US11473126
申请日：2006-06-23
申请人： Toshiyuki Miyauchi , Yuichi Mizutani
发明人： Toshiyuki Miyauchi , Yuichi Mizutani
IPC分类号： H03D1/00 , H03M13/03
CPC分类号： H03M13/4176 , H03M13/4169 , H03M13/6502
摘要： The present invention can reduce power consumption at the time of tracing. The present invention provides a viterbi decoding apparatus for decoding convolution codes, which includes a path memory unit that stores one of two paths toward respective transition states of a convolution code, as a selected path, for a plurality of continuous time points, a tracing unit that traces a selected path stored in the path memory unit in a reversed-time direction, thereby decoding a convolution code at respective time points, each of the time points being prior to a predetermined trace-skipping period, and a control unit that controls the path memory unit, wherein the path memory unit has a storage area designed to store selected paths assuming respective transition states at respective time points, the storage area is divided into sub-areas from the lowest order of transition state, each of the sub-areas corresponding to predetermined number of bits, and reading data can be stopped for each sub-area, and the control unit designates sub-areas from which no selected path needs to be read at respective time points so as to stop reading data from the designated sub-areas.
摘要翻译：本发明可以减少跟踪时的功耗。本发明提供了一种用于对卷积码进行解码的维特比解码装置，其包括路径存储单元，该路径存储单元存储朝向卷积码的各自转换状态的两条路径之一作为多个连续时间点的选定路径，跟踪单元其沿着反向时间方向跟踪存储在路径存储器单元中的所选择的路径，从而在各个时间点对每个时间点进行解码，每个时间点在预定的跳闸周期之前，以及控制单元，路径存储单元，其中，路径存储单元具有被设计为存储在各个时间点处各自的过渡状态的所选择的路径的存储区域，所述存储区域被划分为从过渡状态的最低阶的子区域，每个子区域对应于预定位数，并且可以针对每个子区域停止读取数据，并且控制单元指定没有选择的路径n的子区域在各个时间点读取数据，以停止从指定的子区域读取数据。

9. 发明授权

US07180968B2 Soft-output decoding 失效
标题翻译：软输出解码
公开(公告)号：US07180968B2
公开(公告)日：2007-02-20
申请号：US10111724
申请日：2001-08-31
申请人： Toshiyuki Miyauchi , Kouhei Yamamoto
发明人： Toshiyuki Miyauchi , Kouhei Yamamoto
IPC分类号： H03D1/00
CPC分类号： H03M13/2957 , H03M13/27 , H03M13/2903 , H03M13/6566
摘要： To appropriately express an erasure position of a code by a small-scale, simple-structured circuit, a soft-output decoding circuit (90) in each element decoder includes a received value and a priori probability information selection circuit (154) to select an input to-be-decoded received value TSR and extrinsic information or interleaved data TEXT, whichever is necessary for soft-output decoding. Based on inner erasure position information IERS supplied from an inner erasure information generating circuit (152), the received value and a priori probability information selection circuit (154) replaces a position where no coded output exists due to puncture or the like with a symbol whose likelihood is “0”. That is, the received value and a priori probability information selection circuit (154) outputs information which assures a probability in which a bit corresponding to a position where there is no coded output is “0” or “1” to be “½”.
摘要翻译：为了通过小规模，简单的结构化电路适当地表示代码的擦除位置，每个元件解码器中的软输出解码电路（90）包括接收值和先验概率信息选择电路（154），以选择输入待解码的接收值TSR和外部信息或交织数据TEXT，以软输出解码为准。基于从内部擦除信息生成电路（152）提供的内部擦除位置信息IERS，接收到的值和先验概率信息选择电路（154）用一个符号代替由于穿孔等而不存在编码输出的位置，可能性为“0”。也就是说，接收的值和先验概率信息选择电路（154）输出确定与没有编码输出的位置相对应的位为“0”或“1”的概率的信息。

10. 发明申请

US20050010848A1 Encoding device, encoding method, encoding method program, decoding device, decoding method, decoding method program 失效
标题翻译：编码装置，编码方法，编码方法程序，解码装置，解码方法，解码方法程序
公开(公告)号：US20050010848A1
公开(公告)日：2005-01-13
申请号：US10498936
申请日：2003-10-08
申请人： Takashi Yokokawa , Toshiyuki Miyauchi , Yasuhiro Iida , Kohei Yamamoto , Masayuki Hattori
发明人： Takashi Yokokawa , Toshiyuki Miyauchi , Yasuhiro Iida , Kohei Yamamoto , Masayuki Hattori
IPC分类号： G06F11/10 , H03M13/23 , H03M13/25 , H03M13/27 , H03M13/29 , H04L1/00 , H03M13/00
CPC分类号： H04L1/006 , H03M13/25 , H03M13/258 , H03M13/27 , H03M13/29 , H03M13/2972 , H04L1/0055 , H04L1/0065 , H04L1/0071
摘要： The present invention is particularly applied to serial concatenated coding and serial concatenated trellis coded modulation. In second encoding 107, which is inner coding, a sequence that is not encoded or that is encoded so as to produce a finite impulse response and a sequence that is encoded so as to produce an infinite impulse response are output. In interleaving 106 before the second encoding 107, the sequences are permuted so as not to be mixed with each other.
摘要翻译：本发明特别适用于串联编码和串行级联网格编码调制。在作为内部编码的第二编码器107中，输出未被编码或编码以产生有限脉冲响应的序列和被编码以产生无限脉冲响应的序列。在第二编码107之前的交织106中，将这些序列置换为不相互混合。

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