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    • 1. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20100276762A1
    • 2010-11-04
    • US12836826
    • 2010-07-15
    • Masahiro HAYASHITakahisa AKIBAKunio WATANABETomo TAKASOSusumu KENMOCHI
    • Masahiro HAYASHITakahisa AKIBAKunio WATANABETomo TAKASOSusumu KENMOCHI
    • H01L29/78
    • H01L29/7834H01L23/5225H01L23/585H01L29/0638H01L29/0653H01L29/0692H01L29/1083H01L29/402H01L29/7833H01L2924/0002H01L2924/00
    • A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
    • 一种半导体器件,包括:半导体层; 栅极绝缘层; 栅电极; 一个通道区域 源区和漏区; 护环区; 偏移绝缘层; 第一层间电介质; 第一屏蔽层,其形成在所述第一层间电介质和所述保护环区域上方并电连接到所述保护环区域; 第二层间电介质; 以及形成在所述第二层间电介质上方的第二屏蔽层,其中当从所述顶侧观察时,所述第一屏蔽层设置在所述栅电极的两端的沟道宽度方向的外侧; 并且其中所述第二屏蔽层设置在第一区域和/或第二区域的至少一部分的至少一部分中,所述第一区域是所述栅电极的一个边缘与所述第一屏蔽层的与所述第一屏蔽层的边缘相反的边缘之间的区域 所述栅电极的边缘在从所述顶侧观察时在所述沟道宽度方向上,所述第二区域是所述栅电极的另一边缘与所述第一屏蔽层的与所述栅电极的另一边缘相反的边缘之间的区域 在从顶侧观察的通道宽度方向上。
    • 2. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08354728B2
    • 2013-01-15
    • US12836826
    • 2010-07-15
    • Masahiro HayashiTakahisa AkibaKunio WatanabeTomo TakasoSusumu Kenmochi
    • Masahiro HayashiTakahisa AkibaKunio WatanabeTomo TakasoSusumu Kenmochi
    • H01L29/76H01L29/94H01L29/788H01L27/148H01L29/768
    • H01L29/7834H01L23/5225H01L23/585H01L29/0638H01L29/0653H01L29/0692H01L29/1083H01L29/402H01L29/7833H01L2924/0002H01L2924/00
    • A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
    • 一种半导体器件,包括:半导体层; 栅极绝缘层; 栅电极; 一个通道区域 源区和漏区; 护环区; 偏移绝缘层; 第一层间电介质; 第一屏蔽层,其形成在所述第一层间电介质和所述保护环区域上方并电连接到所述保护环区域; 第二层间电介质; 以及形成在所述第二层间电介质上方的第二屏蔽层,其中当从所述顶侧观察时,所述第一屏蔽层设置在所述栅电极的两端的沟道宽度方向的外侧; 并且其中所述第二屏蔽层设置在第一区域和/或第二区域的至少一部分的至少一部分中,所述第一区域是所述栅电极的一个边缘与所述第一屏蔽层的与所述第一屏蔽层的边缘相反的边缘之间的区域 所述栅电极的边缘在从所述顶侧观察时在所述沟道宽度方向上,所述第二区域是所述栅电极的另一边缘与所述第一屏蔽层的与所述栅电极的另一边缘相反的边缘之间的区域 在从顶侧观察的通道宽度方向上。
    • 3. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20080237747A1
    • 2008-10-02
    • US12129191
    • 2008-05-29
    • Masahiro HAYASHITakahisa AKIBAKunio WATANABETomo TAKASOSusumu KENMOCHI
    • Masahiro HAYASHITakahisa AKIBAKunio WATANABETomo TAKASOSusumu KENMOCHI
    • H01L29/00
    • H01L29/7834H01L23/5225H01L23/585H01L29/0638H01L29/0653H01L29/0692H01L29/1083H01L29/402H01L29/7833H01L2924/0002H01L2924/00
    • A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
    • 一种半导体器件,包括:半导体层; 栅极绝缘层; 栅电极; 一个通道区; 源区和漏区; 护环区; 偏移绝缘层; 第一层间电介质; 第一屏蔽层,其形成在所述第一层间电介质和所述保护环区域上方并电连接到所述保护环区域; 第二层间电介质; 以及形成在所述第二层间电介质上方的第二屏蔽层,其中当从所述顶侧观察时,所述第一屏蔽层设置在所述栅电极的两端的沟道宽度方向的外侧; 并且其中所述第二屏蔽层设置在第一区域和/或第二区域的至少一部分的至少一部分中,所述第一区域是所述栅电极的一个边缘与所述第一屏蔽层的与所述第一屏蔽层的边缘相反的边缘之间的区域 所述栅电极的边缘在从所述顶侧观察时在所述沟道宽度方向上,所述第二区域是所述栅电极的另一边缘与所述第一屏蔽层的与所述栅电极的另一边缘相反的边缘之间的区域 在从顶侧观察的通道宽度方向上。
    • 6. 发明申请
    • Semiconductor device
    • 半导体器件
    • US20070057280A1
    • 2007-03-15
    • US11519169
    • 2006-09-11
    • Masahiro HayashiTakahisa AkibaKunio WatanabeTomo TakasoSusumu Kenmochi
    • Masahiro HayashiTakahisa AkibaKunio WatanabeTomo TakasoSusumu Kenmochi
    • H01L29/74
    • H01L29/7834H01L23/5225H01L23/585H01L29/0638H01L29/0653H01L29/0692H01L29/1083H01L29/402H01L29/7833H01L2924/0002H01L2924/00
    • A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
    • 一种半导体器件,包括:半导体层; 栅极绝缘层; 栅电极; 一个通道区; 源区和漏区; 护环区; 偏移绝缘层; 第一层间电介质; 第一屏蔽层,其形成在所述第一层间电介质和所述保护环区域上方并电连接到所述保护环区域; 第二层间电介质; 以及形成在所述第二层间电介质上方的第二屏蔽层,其中当从所述顶侧观察时,所述第一屏蔽层设置在所述栅电极的两端的沟道宽度方向的外侧; 并且其中所述第二屏蔽层设置在第一区域和/或第二区域的至少一部分的至少一部分中,所述第一区域是所述栅电极的一个边缘与所述第一屏蔽层的与所述第一屏蔽层的边缘相反的边缘之间的区域 所述栅电极的边缘在从所述顶侧观察时在所述沟道宽度方向上,所述第二区域是所述栅电极的另一边缘与所述第一屏蔽层的与所述栅电极的另一边缘相反的边缘之间的区域 在从顶侧观察的通道宽度方向上。
    • 7. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07906821B2
    • 2011-03-15
    • US12129191
    • 2008-05-29
    • Masahiro HayashiTakahisa AkibaKunio WatanabeTomo TakasoSusumu Kenmochi
    • Masahiro HayashiTakahisa AkibaKunio WatanabeTomo TakasoSusumu Kenmochi
    • H01L29/76H01L29/94H01L29/788H01L27/148H01L29/768
    • H01L29/7834H01L23/5225H01L23/585H01L29/0638H01L29/0653H01L29/0692H01L29/1083H01L29/402H01L29/7833H01L2924/0002H01L2924/00
    • A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
    • 一种半导体器件,包括:半导体层; 栅极绝缘层; 栅电极; 一个通道区; 源区和漏区; 护环区; 偏移绝缘层; 第一层间电介质; 第一屏蔽层,其形成在所述第一层间电介质和所述保护环区域上方并电连接到所述保护环区域; 第二层间电介质; 以及形成在所述第二层间电介质上方的第二屏蔽层,其中当从所述顶侧观察时,所述第一屏蔽层设置在所述栅电极的两端的沟道宽度方向的外侧; 并且其中所述第二屏蔽层设置在第一区域和/或第二区域的至少一部分的至少一部分中,所述第一区域是所述栅电极的一个边缘与所述第一屏蔽层的与所述第一屏蔽层的边缘相反的边缘之间的区域 所述栅电极的边缘在从所述顶侧观察时在所述沟道宽度方向上,所述第二区域是所述栅电极的另一边缘与所述第一屏蔽层的与所述栅电极的另一边缘相反的边缘之间的区域 在从顶侧观察的通道宽度方向上。
    • 8. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07394137B2
    • 2008-07-01
    • US11519169
    • 2006-09-11
    • Masahiro HayashiTakahisa AkibaKunio WatanabeTomo TakasoSusumu Kenmochi
    • Masahiro HayashiTakahisa AkibaKunio WatanabeTomo TakasoSusumu Kenmochi
    • H01L29/76H01L29/94H01L31/062
    • H01L29/7834H01L23/5225H01L23/585H01L29/0638H01L29/0653H01L29/0692H01L29/1083H01L29/402H01L29/7833H01L2924/0002H01L2924/00
    • A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
    • 一种半导体器件,包括:半导体层; 栅极绝缘层; 栅电极; 一个通道区; 源区和漏区; 护环区; 偏移绝缘层; 第一层间电介质; 第一屏蔽层,其形成在所述第一层间电介质和所述保护环区域上方并电连接到所述保护环区域; 第二层间电介质; 以及形成在所述第二层间电介质上方的第二屏蔽层,其中当从所述顶侧观察时,所述第一屏蔽层设置在所述栅电极的两端的沟道宽度方向的外侧; 并且其中所述第二屏蔽层设置在第一区域和/或第二区域的至少一部分的至少一部分中,所述第一区域是所述栅电极的一个边缘与所述第一屏蔽层的与所述第一屏蔽层的边缘相反的边缘之间的区域 所述栅电极的边缘在从所述顶侧观察时在所述沟道宽度方向上,所述第二区域是所述栅电极的另一边缘与所述第一屏蔽层的与所述栅电极的另一边缘相反的边缘之间的区域 在从顶侧观察的通道宽度方向上。