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1. 发明授权

US06235584B1 Method and system for reducing short channel effects in a memory device 有权
标题翻译：用于减少存储器件中的短通道效应的方法和系统
公开(公告)号：US06235584B1
公开(公告)日：2001-05-22
申请号：US09412544
申请日：1999-10-05
申请人： Yu Sun , Mark T. Ramsbey , Tommy Hsiao
发明人： Yu Sun , Mark T. Ramsbey , Tommy Hsiao
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/66659 , H01L29/7835
摘要： A method and system for providing a semiconductor memory device is disclosed. The method and system include providing a plurality of gate stacks above a substrate. Each of the plurality of gate stacks includes a first edge and a second edge. The method and system also include providing a source implant adjacent to the first edge of each of the plurality of gate stacks and driving the source implant under the first edge of each of the plurality of gate stacks. The method and system also include providing a first spacer and a second spacer for each of the plurality of gate stacks. The first and second spacers are disposed along the first and second edges, respectively, of each of the plurality of gate stacks. The method and system also include providing a drain implant after source implant is driven under the first edge and after the first and second spacers are provided. The drain implant is in the substrate adjacent to the second spacer.
摘要翻译：公开了一种用于提供半导体存储器件的方法和系统。该方法和系统包括在衬底上方提供多个栅叠层。多个栅极堆叠中的每一个包括第一边缘和第二边缘。该方法和系统还包括提供与多个栅极堆叠中的每一个的第一边缘相邻的源极注入，并且在多个栅极堆叠中的每一个的第一边缘的下方驱动源极注入。该方法和系统还包括为多个栅极堆叠中的每一个提供第一间隔物和第二间隔物。第一和第二间隔物分别沿着多个栅极堆叠中的每一个的第一和第二边缘设置。所述方法和系统还包括在源植入物在第一边缘下被驱动并且在提供第一和第二间隔物之后提供漏极注入。漏极注入在与第二间隔物相邻的衬底中。

2. 发明授权

US06747318B1 Buried channel devices and a process for their fabrication simultaneously with surface channel devices to produce transistors and capacitors with multiple electrical gate oxides 有权
标题翻译：掩埋通道器件及其与表面沟道器件同时制造的工艺，以生产具有多个电栅极氧化物的晶体管和电容器
公开(公告)号：US06747318B1
公开(公告)日：2004-06-08
申请号：US10020304
申请日：2001-12-13
申请人： Ravindra M. Kapre , Tommy Hsiao , Yanhua Wang , Kyungjin Min
发明人： Ravindra M. Kapre , Tommy Hsiao , Yanhua Wang , Kyungjin Min
IPC分类号： H01L2994
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823892 , H01L29/7838 , H01L29/94
摘要： A method for fabricating buried channel NMOS devices and the devices themselves are disclosed. These buried channel NMOS devices are fabricated with a p-type substrate, an n-type implant in the top portion (approximately 400 to 1000 Å deep) of the substrate, and an insulating gate dielectric above the n-type implant. An n-type or p-type doped polysilicon gate electrode is formed on top of the insulating gate dielectric. The n-type implant region is doped in such a way that it is depleted of charge carriers when the device's gate electrode is at the same potential as the well (zero bias). When the gate electrode is biased +Ve with respect to the device's well substrate a conducting channel of mobile electrons is formed in a portion of the buried layer. This type of biasing is known as inversion bias since the charge carriers are of the opposite type than the p-well. Under inversion bias, the buried channel silicon region is partially depleted of charge carriers, which effectively adds to the thickness of the gate dielectric layer. A capacitor or transistor fabricated according to this buried channel teaching behaves in a manner electrically equivalent to a capacitor or transistor fabricated with a thicker dielectric. PMOS transistors and capacitors can be constructed according to the present invention in a manner similar to that described for NMOS transistors and capacitors by substituting n-type doping for p-type and visa versa. This leads to the fabrication of CMOS devices with multiple effective dielectric thicknesses on the same substrate.
摘要翻译：公开了一种用于制造掩埋沟道NMOS器件和器件本身的方法。这些掩埋沟道NMOS器件由p型衬底，衬底的顶部（约400至1000深）中的n型注入器以及n型注入器之上的绝缘栅极电介质制成。在绝缘栅极电介质的顶部上形成n型或p型掺杂多晶硅栅电极。掺杂n型注入区的方式是当器件的栅电极处于与阱相同的电位（零偏压）时，其耗尽电荷载流子。当栅电极相对于器件的阱衬底偏置+ Ve时，移动电子的导电沟道形成在掩埋层的一部分中。这种偏置称为反向偏置，因为电荷载体与p阱相反。在反向偏置下，掩埋沟道硅区域部分耗尽电荷载流子，这有效地增加了栅极介电层的厚度。根据该掩埋通道示教制造的电容器或晶体管以与电介质较厚的电容器或晶体管电气等效的方式起作用。根据本发明，PMOS晶体管和电容器可以以类似于对NMOS晶体管和电容器描述的方式构造，通过用n型掺杂代替p型，反之亦然。这导致在同一衬底上制造具有多个有效介电厚度的CMOS器件。

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