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1. 发明申请

US20080109707A1 FORWARD ERROR CORRECTION ENCODING FOR MULTIPLE LINK TRANSMISSION CAPATIBLE WITH 64B/66B SCRAMBLING 有权
标题翻译：使用64B / 66B SCRAMBLING插入多个链路传输的前向纠错编码
公开(公告)号：US20080109707A1
公开(公告)日：2008-05-08
申请号：US11556240
申请日：2006-11-03
申请人： Timothy Dell , Rene Glaise
发明人： Timothy Dell , Rene Glaise
IPC分类号： H03M13/00
CPC分类号： H04L25/03866 , H03M13/03 , H03M13/27 , H04L1/0042 , H04L1/0057 , H04L1/0071
摘要： A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable. In addition, the packet can be transported across multiple serial links for higher bandwidth applications without a degradation of the code efficiency. The Hamming code can be generated from any irreducible polynomial, such as H(x)=x10+x3+1. The BIP code is chosen to be of degree 6 to fit with 64B/66B scrambling polynomial and is represented by B(x)=x6+1.
摘要翻译：与由串行器/解串器（SerDes）通信信道链路传输的64B / 66B编码标准使用的自同步扰频器兼容的前向纠错（FEC）码。 FEC码分别允许在加扰之前和之后进行编码和解码，以便保留对发射信号的加扰操作的性质。尽管由于64B / 66B扰频处理而导致的所有传输错误中的三倍乘以，该代码允许校正任何单个传输错误。汉明码与程度n（BIP-n）的比特交错奇偶校验码组合。这两个代码提供了对于分组的最大长度中的任何位置的错误以及通过解扰过程复制两次或三次的错误的保护。所有单个位错误（无论是否增加）都有独特的综合征，因此易于修正。此外，分组可以跨多个串行链路传输，以实现更高带宽的应用，而不会降低代码效率。汉明码可以从任何不可约的多项式（例如H（x）= x±10 + x 3 + 1）生成。 BIP码被选择为6度以适应64B / 66B加扰多项式，并且由B（x）= x6 + 1表示。

2. 发明申请

US20080046796A1 SYSTEM, METHOD AND STORAGE MEDIUM FOR PROVIDING FAULT DETECTION AND CORRECTION IN A MEMORY SUBSYSTEM 有权
标题翻译：用于提供记忆子系统中的故障检测和校正的系统，方法和存储介质
公开(公告)号：US20080046796A1
公开(公告)日：2008-02-21
申请号：US11851527
申请日：2007-09-07
申请人： Timothy Dell , Kevin Gower , Warren Maule
发明人： Timothy Dell , Kevin Gower , Warren Maule
IPC分类号： H03M13/00
CPC分类号： G11C5/04
摘要： A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.
摘要翻译：具有存储器总线和存储器组件的存储器子系统。存储器总线包括多个位线。存储器组件与存储器总线通信，并且包括用于经由存储器总线接收多个分组中的错误代码校正（ECC）字的指令。 ECC字包括排列成多个多位ECC符号的数据位和ECC位。每个ECC符号与存储器总线上的位线之一相关联。存储器组件还包括用于利用ECC符号之一对经由与ECC符号相关联的位层接收的ECC字中的比特进行错误检测和校正的指令。

3. 发明申请

US20080046795A1 SYSTEM, METHOD AND STORAGE MEDIUM FOR PROVIDING FAULT DETECTION AND CORRECTION IN A MEMORY SUBSYSTEM 有权
公开(公告)号：US20080046795A1
公开(公告)日：2008-02-21
申请号：US11851496
申请日：2007-09-07
申请人： Timothy Dell , Kevin Gower , Warren Maule
发明人： Timothy Dell , Kevin Gower , Warren Maule
IPC分类号： H03M13/00
CPC分类号： G11C5/04
摘要： A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.

4. 发明申请

US20060179362A1 Double DRAM bit steering for multiple error corrections 失效
标题翻译：双重DRAM位转向可进行多次错误更正
公开(公告)号：US20060179362A1
公开(公告)日：2006-08-10
申请号：US11054417
申请日：2005-02-09
申请人： Luiz Alves , Mark Brittain , Timothy Dell , Sanjeev Ghai , Warren Maule , Scott Swaney
发明人： Luiz Alves , Mark Brittain , Timothy Dell , Sanjeev Ghai , Warren Maule , Scott Swaney
IPC分类号： G06F11/00
CPC分类号： G11C29/42 , G06F11/1044 , G11C5/04 , G11C29/4401 , G11C29/76 , G11C29/846 , G11C2029/0409
摘要： A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 0:3) and a right half (for storing bits 4:7). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM's defective half are made to a half of a spare DRAM in the DIMM, while the DRAM's non-defective half continues to be used for subsequently storing data.
摘要翻译：提出了一种用于校正双列直插式存储器模块（DIMM）中的主动态随机存取存储器（DRAM）中的数据错误的方法和系统。每个DRAM具有左半部分（用于存储位0：3）和右半部分（用于存储位4：7）。确定数据错误是在主DRAM的左半还是右半部。发生错误的主要DRAM的一半从服务中删除。原始存储在主DRAM缺陷半部分的数据的所有后续读取和写入都被制成DIMM中的备用DRAM的一半，而DRAM的无缺陷半部分继续用于随后存储数据。

5. 发明申请

US20060107175A1 System, method and storage medium for providing fault detection and correction in a memory subsystem 失效
公开(公告)号：US20060107175A1
公开(公告)日：2006-05-18
申请号：US10977914
申请日：2004-10-29
申请人： Timothy Dell , Kevin Gower , Warren Maule
发明人： Timothy Dell , Kevin Gower , Warren Maule
IPC分类号： H03M13/00
CPC分类号： G11C5/04
摘要： A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.

6. 发明申请

US20060036827A1 System, method and storage medium for providing segment level sparing 有权
公开(公告)号：US20060036827A1
公开(公告)日：2006-02-16
申请号：US10903188
申请日：2004-07-30
申请人： Timothy Dell , Frank Ferraiolo , Kevin Gower , Kevin Kark , Mark Kellogg , Warren Maule
发明人： Timothy Dell , Frank Ferraiolo , Kevin Gower , Kevin Kark , Mark Kellogg , Warren Maule
IPC分类号： G06F12/00
CPC分类号： G06F11/201 , G06F11/104
摘要： A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.

7. 发明授权

US07996747B2 Forward error correction encoding for multiple link transmission compatible with 64B/66B scrambling 有权
标题翻译：用于与64B / 66B加扰兼容的多链路传输的前向纠错编码
公开(公告)号：US07996747B2
公开(公告)日：2011-08-09
申请号：US11556240
申请日：2006-11-03
申请人： Timothy Dell , Rene Glaise
发明人： Timothy Dell , Rene Glaise
IPC分类号： H03M13/00
CPC分类号： H04L25/03866 , H03M13/03 , H03M13/27 , H04L1/0042 , H04L1/0057 , H04L1/0071
摘要： A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable. In addition, the packet can be transported across multiple serial links for higher bandwidth applications without a degradation of the code efficiency. The Hamming code can be generated from any irreducible polynomial, such as H(x)=x10+x3+1. The BIP code is chosen to be of degree 6 to fit with 64B/66B scrambling polynomial and is represented by B(x)=x6+1.
摘要翻译：与由串行器/解串器（SerDes）通信信道链路传输的64B / 66B编码标准使用的自同步扰频器兼容的前向纠错（FEC）码。 FEC码分别允许在加扰之前和之后进行编码和解码，以便保留对发射信号的加扰操作的性质。尽管由于64B / 66B扰频处理而导致的所有传输错误中的三倍乘以，该代码允许校正任何单个传输错误。汉明码与程度n（BIP-n）的比特交错奇偶校验码组合。这两个代码提供了对于分组的最大长度中的任何位置的错误以及通过解扰过程复制两次或三次的错误的保护。所有单个位错误（无论是否增加）都有独特的综合征，因此易于修正。此外，分组可以跨多个串行链路传输，以实现更高带宽的应用，而不会降低代码效率。汉明码可以从任何不可约的多项式生成，如H（x）= x10 + x3 + 1。 BIP码被选择为6度以适应64B / 66B加扰多项式，并由B（x）= x6 + 1表示。

8. 发明申请

US20070300129A1 SYSTEM, METHOD AND STORAGE MEDIUM FOR PROVIDING FAULT DETECTION AND CORRECTION IN A MEMORY SUBSYSTEM 有权
标题翻译：用于提供记忆子系统中的故障检测和校正的系统，方法和存储介质
公开(公告)号：US20070300129A1
公开(公告)日：2007-12-27
申请号：US11851485
申请日：2007-09-07
申请人： Timothy Dell , Kevin Gower , Warren Maule
发明人： Timothy Dell , Kevin Gower , Warren Maule
IPC分类号： G11C29/52
CPC分类号： G11C5/04
摘要： A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.
摘要翻译：具有存储器总线和存储器组件的存储器子系统。存储器总线包括多个位线。存储器组件与存储器总线通信，并且包括用于经由存储器总线接收多个分组中的错误代码校正（ECC）字的指令。 ECC字包括排列成多个多位ECC符号的数据位和ECC位。每个ECC符号与存储器总线上的位线之一相关联。存储器组件还包括用于利用ECC符号之一对经由与ECC符号相关联的位层接收的ECC字中的比特进行错误检测和校正的指令。

9. 发明申请

US20060036826A1 System, method and storage medium for providing a bus speed multiplier 审中-公开
标题翻译：用于提供总线速度倍增器的系统，方法和存储介质
公开(公告)号：US20060036826A1
公开(公告)日：2006-02-16
申请号：US10903182
申请日：2004-07-30
申请人： Timothy Dell , Kevin Gower , Kevin Kark , Mark Kellogg , Warren Maule
发明人： Timothy Dell , Kevin Gower , Kevin Kark , Mark Kellogg , Warren Maule
IPC分类号： G06F12/00
CPC分类号： G06F13/4243 , G06F13/1684
摘要： A memory subsystem for providing a bus speed multiplier. The memory subsystem includes one or more memory modules operating at a memory module data rate. The memory subsystem also includes a memory controller and one or more memory busses. The memory busses operate at four times the memory module data rate. The memory controller and the memory modules are interconnected by a packetized multi-transfer interface via the memory busses.
摘要翻译：用于提供总线速度倍增器的存储器子系统。存储器子系统包括以存储器模块数据速率操作的一个或多个存储器模块。存储器子系统还包括存储器控制器和一个或多个存储器总线。存储器总线的操作是内存模块数据速率的四倍。存储器控制器和存储器模块通过分组化的多传输接口经由存储器总线互连。

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