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1. 发明授权

US4183123A Yarn texturing apparatus 失效
标题翻译：纱线变形装置
公开(公告)号：US4183123A
公开(公告)日：1980-01-15
申请号：US860909
申请日：1977-12-15
申请人： Kenzo Tanaka , Tetsuhiko Endo
发明人： Kenzo Tanaka , Tetsuhiko Endo
IPC分类号： D02J1/00 , D02G1/16 , D02J1/02
CPC分类号： D02G1/161
摘要： Disclosed is a yarn texturing apparatus for producing a multifilament yarn containing complex interfilament entanglement, comprising a housing having inlet and outlet ends connected by a yarn passage, a turbulence section in the yarn passage, an exit orifice constituting the yarn outlet and communicating with the turbulence section and means for introducing pressurized gas into the yarn passage, which is improved by providing a yarn guide for separating a multifilament yarn blown out of the exit orifice from blown gas while guiding the yarn along a guide surface of the yarn guide. The yarn guide is provided outside of the housing and in the proximity of the exit end of the orifice, in a condition such that the yarn guide does not cross the center-line of the exit orifice and the guide surface of the yarn guide faces the yarn outlet end surface of the housing.
摘要翻译：公开了一种用于生产含有复合纤维缠结的复丝纱线的纱线织造装置，其包括具有通过纱线通道连接的入口端和出口端的壳体，纱线通道中的湍流部分，构成出纱口的出口孔与湍流连通该部分和装置用于将加压气体引入到纱线通道中，这通过提供一种用于将从出口孔吹出的复丝纱线从吹气中分离的导丝器而改进，同时沿着导纱器的引导表面引导纱线。导丝器设置在壳体的外部并且在孔口的出口端附近，在导纱器不与出口孔的中心线交叉的状态下，导纱器的引导面面向纱线出口端面的外壳。

2. 发明授权

US07937645B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07937645B2
公开(公告)日：2011-05-03
申请号：US11443109
申请日：2006-05-31
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G11C29/00
CPC分类号： G11C29/42
摘要： A conversion control unit sets a converting function of a write data conversion unit or a read data conversion unit enabled or disabled for each controller. Accordingly, for a controller which needs original external data, the external data can be inputted and outputted, whereas for a controller which needs converted internal data, the internal data can be inputted and outputted. A data converting function of a conventional controller can be realized in a semiconductor memory, which can reduce the load on the controller. As a result, the performance of a system can be improved. A disabled controller which has no access right cannot read correct data (original data before conversion). Hence, the security of data written into the semiconductor memory can be protected.
摘要翻译：转换控制单元设置对每个控制器启用或禁用的写数据转换单元或读数据转换单元的转换功能。因此，对于需要原始外部数据的控制器，可以输入和输出外部数据，而对于需要转换的内部数据的控制器，可以输入和输出内部数据。可以在半导体存储器中实现传统控制器的数据转换功能，这可以减少控制器上的负载。结果，可以提高系统的性能。无权访问的无效控制器无法读取正确的数据（转换前的原始数据）。因此，可以保护写入半导体存储器的数据的安全性。

3. 发明授权

US4116393A Apparatus for collecting and preparing sample yarns to be tested 失效
标题翻译：用于收集和制备待测试样品纱线的装置
公开(公告)号：US4116393A
公开(公告)日：1978-09-26
申请号：US841052
申请日：1977-10-11
申请人： Yoshinori Inouye , Hiromitsu Kanamori , Nobuo Tsuchida , Syozo Morishita , Tetsuhiko Endo
发明人： Yoshinori Inouye , Hiromitsu Kanamori , Nobuo Tsuchida , Syozo Morishita , Tetsuhiko Endo
IPC分类号： B65H51/22 , B65H61/00 , B65H63/032 , B65H69/00 , D01H13/32 , G01N1/02 , G01N33/36 , B65H54/00 , G01L5/04
CPC分类号： G01N33/365 , B65H51/22 , B65H63/0324 , B65H69/00 , G01N1/02 , B65H2513/112 , B65H2701/31
摘要： A sample yarn-collecting apparatus for preparing a continuous yarn knotted in an end-to-end manner, in which sample yarns having a certain length are collected from a plurality of yarn packages, each of them are connected in succession in an end-to-end manner to obtain one continuous yarn, and the continuous yarn is wound temporarily and thereafter continuously unwound to be fed to testing means while storing it in a quantity within a predetermined range, is disclosed. This apparatus comprises sample yarn collecting means for collecting sample yarns from packages and connecting each of them to form one continuous yarn, means for storing the continuous yarn fed from said collecting means on a rotary member by winding it and feeding the continuous yarn wound and stored on the rotary member to testing means by unwinding it, and supplementary means for controlling the above two means.
摘要翻译：一种用于制备以多个纱线卷装收集具有一定长度的样品纱线的端对端方式编织的连续纱线的样品纱线收集装置，它们中的每一个连续地连续地连接到以连续的方式获得一条连续的纱线，并且连续纱线被暂时缠绕，然后连续地展开以供给测试装置，同时将其保持在预定范围内的量。该装置包括用于从包装件收集样品纱线并连接它们以形成一根连续纱线的样品纱线收集装置，用于将从所述收集装置馈送的连续纱线通过缠绕并将其卷绕并存储的连续纱线在旋转构件上通过展开测试装置，以及用于控制上述两种装置的补充装置。

4. 发明授权

US4040240A Method and apparatus for doubling and twisting a yarn by a two-step changeover system 失效
标题翻译：通过两步转换系统对纱线进行加捻和扭转的方法和装置
公开(公告)号：US4040240A
公开(公告)日：1977-08-09
申请号：US713851
申请日：1976-08-12
申请人： Kotaro Fujioka , Osami Tsuchihashi , Tetsuhiko Endo , Masakazu Hirota
发明人： Kotaro Fujioka , Osami Tsuchihashi , Tetsuhiko Endo , Masakazu Hirota
IPC分类号： D01H7/74 , D02G3/28 , D01H1/08
CPC分类号： D02G3/283
摘要： A method and apparatus for doubling and twisting a material yarn by a two-step changeover system by utilizing a pot twisting and winding device is disclosed. To produce a doubled and twisted yarn having a yarn configuration of two component yarns forming the yarn in a balanced condition, when the second step operation is carried out so as to double a primary twisted yarn of a yarn package formed in the pot by a first step operation with a yarn fed from a supply source and twist this doubled yarn while eliminating the primary twists imparted to the material yarn, the position of the bottom end of the traverse tube in the pot must be controlled so as to satisfy a particular condition D.sub.2 .gtoreq. L.sub.2, where D.sub.2 represents an inside diameter of the full size yarn package formed in the pot by the first step operation, while L.sub.2 represents a distance between the bottom end of the traverse tube and an inside bottom surface of the pot.
摘要翻译：公开了一种通过利用锅加捻和缠绕装置通过两步切换系统来加捻和扭转材料纱线的方法和装置。为了制造在平衡状态下具有形成纱线的双组分纱线的纱线构型的双重加捻纱线，当进行第二步骤操作以便将形成在所述盆中的纱线卷装的第一加捻纱线加倍时，使用从供应源供给的纱线进行步进操作，并扭转该双纱，同时消除了赋予材料纱线的初级扭曲，必须控制横管的底端位于罐中的位置以满足特定条件D2 > / = L2，其中D2表示通过第一步骤操作在罐中形成的全尺寸纱线卷装的内径，而L2表示横动管的底端和罐的内底面之间的距离。

5. 发明授权

US07561455B2 Memory system using single wavelength optical transmission 有权
标题翻译：内存系统采用单波长光传输
公开(公告)号：US07561455B2
公开(公告)日：2009-07-14
申请号：US11498175
申请日：2006-08-03
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G11C13/04
CPC分类号： G06F13/4072
摘要： A controller converts a parallel command signal and address signal, or a parallel write data signal into a first serial signal, and outputs the converted signal as a first optical signal with a single wavelength to a memory device via an optical transmission line. The memory device converts the first optical signal into the original parallel command signal, address signal, and write data signal, and outputs the converted parallel signals to a memory unit. The memory device converts a parallel read data signal from the memory unit into a second serial signal, and outputs the converted signal to the controller via the optical transmission line as a second optical signal with a single wavelength. It is unnecessary to transmit the optical signal using an optical multiplexer, an optical demultiplexer, etc., thereby improving transmission rate of signals transmitted between the controller and the memory device at minimum cost.
摘要翻译：控制器将并行命令信号和地址信号或并行写入数据信号转换为第一串行信号，并将转换的信号作为具有单一波长的第一光信号通过光传输线输出到存储器件。存储器件将第一光信号转换为原始并行命令信号，地址信号和写数据信号，并将转换的并行信号输出到存储器单元。存储器装置将来自存储器单元的并行读取数据信号转换为第二串行信号，并且经由光传输线路将转换的信号作为具有单个波长的第二光信号输出到控制器。不需要使用光复用器，光解复用器等来发送光信号，从而以最小的成本提高在控制器和存储器件之间传输的信号的传输速率。

6. 发明申请

US20070230231A1 Memory system 有权
标题翻译：内存系统
公开(公告)号：US20070230231A1
公开(公告)日：2007-10-04
申请号：US11498175
申请日：2006-08-03
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G11C13/04
CPC分类号： G06F13/4072
摘要： A controller converts a parallel command signal and address signal, or a parallel write data signal into a first serial signal, and outputs the converted signal as a first optical signal with a single wavelength to a memory device via an optical transmission line. The memory device converts the first optical signal into the original parallel command signal, address signal, and write data signal, and outputs the converted parallel signals to a memory unit. The memory device converts a parallel read data signal from the memory unit into a second serial signal, and outputs the converted signal to the controller via the optical transmission line as a second optical signal with a single wavelength. It is unnecessary to transmit the optical signal using an optical multiplexer, an optical demultiplexer, etc., thereby improving transmission rate of signals transmitted between the controller and the memory device at minimum cost.
摘要翻译：控制器将并行命令信号和地址信号或并行写入数据信号转换为第一串行信号，并将转换的信号作为具有单一波长的第一光信号通过光传输线输出到存储器件。存储器件将第一光信号转换为原始并行命令信号，地址信号和写数据信号，并将转换的并行信号输出到存储器单元。存储器装置将来自存储器单元的并行读取数据信号转换为第二串行信号，并且经由光传输线路将转换的信号作为具有单个波长的第二光信号输出到控制器。不需要使用光复用器，光解复用器等来发送光信号，从而以最小的成本提高在控制器和存储器件之间传输的信号的传输速率。

7. 发明申请

US20070192664A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20070192664A1
公开(公告)日：2007-08-16
申请号：US11443109
申请日：2006-05-31
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G11C29/00
CPC分类号： G11C29/42
摘要： A conversion control unit sets a converting function of a write data conversion unit or a read data conversion unit enabled or disabled for each controller. Accordingly, for a controller which needs original external data, the external data can be inputted and outputted, whereas for a controller which needs converted internal data, the internal data can be inputted and outputted. A data converting function of a conventional controller can be realized in a semiconductor memory, which can reduce the load on the controller. As a result, the performance of a system can be improved. A disabled controller which has no access right cannot read correct data (original data before conversion). Hence, the security of data written into the semiconductor memory can be protected.
摘要翻译：转换控制单元设置对每个控制器启用或禁用的写数据转换单元或读数据转换单元的转换功能。因此，对于需要原始外部数据的控制器，可以输入和输出外部数据，而对于需要转换的内部数据的控制器，可以输入和输出内部数据。可以在半导体存储器中实现传统控制器的数据转换功能，这可以减少控制器上的负载。结果，可以提高系统的性能。无权访问的无效控制器无法读取正确的数据（转换前的原始数据）。因此，可以保护写入半导体存储器的数据的安全性。

8. 发明申请

US20070189100A1 Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：US20070189100A1
公开(公告)日：2007-08-16
申请号：US11443028
申请日：2006-05-31
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1006
摘要： A memory cell array ARY includes a plurality of sub-arrays SARY. A data transfer unit DTU alternately accesses the sub-arrays SARY to transfer data between the sub-arrays SARY. Accordingly, it is possible to transfer data stored in one of the sub-arrays SARY to another sub-array SARY without outputting the data to a bus connected to a semiconductor memory MEM. For example, a microcontroller CNT in a system MSYS can use the bus during the data transfer since the bus is not used for the data transfer. As a result, it is possible to prevent the performance of the system MSYS from being deteriorated due to the data transfer.
摘要翻译：存储单元阵列ARY包括多个子阵列SARY。数据传输单元DTU交替地访问子阵列SARY以在子阵列SARY之间传送数据。因此，可以将存储在一个子阵列SARY中的数据传送到另一个子阵列SARY，而不将数据输出到连接到半导体存储器MEM的总线。例如，系统MSYS中的微控制器CNT可以在数据传输期间使用总线，因为总线不用于数据传输。结果，可以防止系统MSYS的性能由于数据传输而恶化。

9. 发明申请

US20070189052A1 Memory system 有权
标题翻译：内存系统
公开(公告)号：US20070189052A1
公开(公告)日：2007-08-16
申请号：US11443030
申请日：2006-05-31
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G11C13/04 , G11C7/10 , G11C5/06
CPC分类号： G06F13/4243 , G11C5/066 , G11C7/1006
摘要： A memory controller multiplexes access signals each consisting of a plurality of bits as optical signals and outputs the multiplexed optical signals. At this time, the optical signals whose wavelengths differ depending on memory devices are generated. A memory interface unit demultiplexes the multiplexed optical signals into the original optical signals and converts the demultiplexed optical signals into electrical signals. The memory interface unit determines to which of the memory devices the electrical signals resulting from the conversion should be outputted, according to the wavelengths of the demultiplexed optical signals. This frees the memory controller from a need for transmitting to the memory interface unit a signal for identifying the memory device. The memory interface unit need not include a decoding circuit for identifying the memory device.
摘要翻译：存储器控制器将每个由多个位组成的访问信号复用为光信号并输出复用的光信号。此时，产生根据存储器件波长不同的光信号。存储器接口单元将复用的光信号解复用为原始光信号，并将解复用的光信号转换为电信号。存储器接口单元根据解复用的光信号的波长来确定应该向哪个存储器件输出由转换产生的电信号。这使得存储器控制器不需要向存储器接口单元发送用于识别存储器件的信号。存储器接口单元不需要包括用于识别存储器件的解码电路。

10. 发明授权

US4398386A Process and apparatus for simultaneously drawing and false-twisting thermoplastic synthetic yarn 失效
标题翻译：用于同时拉伸和假捻热塑性合成纱线的方法和装置
公开(公告)号：US4398386A
公开(公告)日：1983-08-16
申请号：US255854
申请日：1981-04-20
申请人： Tetsuhiko Endo , Kunihiko Ueda , Tadashi Kohara
发明人： Tetsuhiko Endo , Kunihiko Ueda , Tadashi Kohara
IPC分类号： D02G1/02 , D02G1/04 , D02G1/16
CPC分类号： D02G1/022
摘要： A process and an apparatus for simultaneously drawing and false-twisting a thermoplastic synthetic yarn, in or by which an undrawn or a partially drawn yarn is drawn under a dry hot condition in a condition of the yarn being false-twisted by twist transmitted from a false-twister and immediately thereafter heat-set under a wet hot condition prior to untwisting.The apparatus includes a yarn heater, which comprises a dry heater disposed on the side of a feeding device for the undrawn or partially drawn yarn and a wet heater on the side of a false-twister along the yarn passing direction.
摘要翻译：一种用于同时拉伸和假捻热塑性合成纱线的方法和装置，其中，在干燥热条件下，在纱线被扭曲的状态下，未拉伸或部分拉伸纱线被拉伸或扭曲，在扭转之前，立即在湿热条件下热定形。该装置包括纱线加热器，其包括设置在用于未拉伸或部分拉伸的纱线的进给装置的侧面的干燥加热器和沿着纱线通过方向的假捻器一侧的湿加热器。

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