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1. 发明授权

US08902676B2 Wordline coupling reduction technique 有权
标题翻译：字线耦合减少技术
公开(公告)号：US08902676B2
公开(公告)日：2014-12-02
申请号：US13457065
申请日：2012-04-26
申请人： TaeHyung Jung , BokMoon Kang
发明人： TaeHyung Jung , BokMoon Kang
IPC分类号： G11C7/10 , G11C5/06 , G11C16/24 , G11C7/12 , G11C16/26 , G11C8/08
CPC分类号： G11C8/08 , G11C5/063 , G11C7/12 , G11C16/24 , G11C16/26
摘要： A semiconductor memory includes a memory array having memory cells coupled to wordlines and bitlines. Each wordline has a left end and an opposing right end. A first wordline in every two adjacent wordlines has its left end connected to a left row driver and its right end connected to a right clamp circuit, and a second wordline in every two adjacent wordlines has its right end connected to a right row driver and its left end connected to a left clamp circuit, such that when the right clamp circuits are activated, the right clamp circuits clamp the corresponding wordline ends to a predetermined potential, and when the left clamp circuits are activated, the left clamp circuits clamp the corresponding wordline ends to the predetermined potential.
摘要翻译：半导体存储器包括具有耦合到字线和位线的存储器单元的存储器阵列。每个字线都有一个左端和一个相反的右端。每两个相邻字线中的第一个字线的左端连接到左行驱动器，其右端连接到右钳位电路，每两个相邻字线中的第二个字线的右端连接到右排驱动器，左端连接到左钳位电路，使得当右钳位电路被激活时，右钳位电路将相应的字线端钳位到预定电位，并且当左钳位电路被激活时，左钳位电路钳位相应的字线结束到预定的电位。

2. 发明申请

US20140022856A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体器件和半导体存储器件
公开(公告)号：US20140022856A1
公开(公告)日：2014-01-23
申请号：US13551147
申请日：2012-07-17
申请人： Taehyung JUNG , Kwanweon Kim
发明人： Taehyung JUNG , Kwanweon Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C16/20 , G11C29/785 , G11C29/82 , G11C2029/4402
摘要： A semiconductor device includes a non-volatile memory unit, a data line configured to transfer data sequentially outputted from the non-volatile memory unit, and a shift register unit configured to include a plurality of registers that shift and store the data transferred through the data line in synchronization with a clock. The semiconductor device includes a non-volatile memory unit having an e-fuse array, and transfers the data stored in an e-fuse array to other constituent elements of the semiconductor device that use the data of the e-fuse array in order to have the data stored in the e-fuse array, including diverse setup information and repair information.
摘要翻译：半导体器件包括非易失性存储器单元，被配置为传送从非易失性存储器单元顺序输出的数据的数据线，以及移位寄存器单元，被配置为包括多个寄存器，用于移位和存储通过数据传送的数据线与时钟同步。半导体器件包括具有电子熔丝阵列的非易失性存储器单元，并将存储在电熔丝阵列中的数据传送到使用电子熔丝阵列的数据的半导体器件的其它组成元件，以便具有存储在电子熔丝阵列中的数据，包括各种设置信息和修复信息。

3. 发明申请

US20140003175A1 STORAGE CELL BRIDGE SCREEN TECHNIQUE 有权
标题翻译：存储池桥接屏幕技术
公开(公告)号：US20140003175A1
公开(公告)日：2014-01-02
申请号：US13540227
申请日：2012-07-02
申请人： TaeHyung Jung , KeeSoo Kim
发明人： TaeHyung Jung , KeeSoo Kim
IPC分类号： G11C7/02 , G11C7/00
CPC分类号： G11C7/02 , G11C7/08 , G11C29/025
摘要： A semiconductor memory includes a circuit block that is configured to receive a test mode command, a first sense amplifier that is coupled to sense and amplify a state of a first memory cell when enabled, and a second sense amplifier that is coupled to sense and amplify a state of a second memory cell when enabled. In an active cycle, the circuit block generates one or more control signals in response to the test mode command that cause the second sense amplifier to be enabled a predetermined amount of time after the first sense amplifier is enabled.
摘要翻译：半导体存储器包括被配置为接收测试模式命令的电路块，耦合以在使能时耦合以感测和放大第一存储器单元的状态的第一读出放大器，以及耦合到感测和放大的第二读出放大器启用时第二存储器单元的状态。在有效周期中，电路块根据测试模式命令产生一个或多个控制信号，该命令使第二读出放大器在第一读出放大器被使能之后能够被预定的时间使能。

4. 发明授权

US08279686B2 Memory circuits, systems, and methods for providing bit line equalization voltages 有权
标题翻译：用于提供位线均衡电压的存储器电路，系统和方法
公开(公告)号：US08279686B2
公开(公告)日：2012-10-02
申请号：US12692512
申请日：2010-01-22
申请人： Kuoyuan Peter Hsu , TaeHyung Jung , Douk Hyoun Ryu , Young Suk Kim
发明人： Kuoyuan Peter Hsu , TaeHyung Jung , Douk Hyoun Ryu , Young Suk Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C11/4076
摘要： A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a first bit line. At least one bit line equalization transistor is coupled between the first bit line and a second bit line. A bit line equalization circuit is coupled with the bit line equalization transistor. The bit line equalization circuit is configured for providing a pulse to the bit line equalization transistor to substantially equalize voltages of the first bit line and the second bit line during a standby period before an access cycle of the memory cell.
摘要翻译：存储电路包括至少一个用于存储表示数据的电荷的存储单元。存储单元与字线和第一位线耦合。至少一个位线均衡晶体管耦合在第一位线和第二位线之间。位线均衡电路与位线均衡晶体管耦合。位线均衡电路被配置为向位线均衡晶体管提供脉冲，以在存储单元的访问周期之前的待机期间基本上均衡第一位线和第二位线的电压。

5. 发明授权

US09728235B2 Semiconductor device and semiconductor memory device 有权
公开(公告)号：US09728235B2
公开(公告)日：2017-08-08
申请号：US13551147
申请日：2012-07-17
申请人： Taehyung Jung , Kwanweon Kim
发明人： Taehyung Jung , Kwanweon Kim
IPC分类号： G01R31/28 , G11C7/10 , G11C16/20 , G11C29/00 , G11C29/44
CPC分类号： G11C7/1006 , G11C16/20 , G11C29/785 , G11C29/82 , G11C2029/4402
摘要： A semiconductor device includes a non-volatile memory unit, a data line configured to transfer data sequentially outputted from the non-volatile memory unit, and a shift register unit configured to include a plurality of registers that shift and store the data transferred through the data line in synchronization with a clock. The semiconductor device includes a non-volatile memory unit having an e-fuse array, and transfers the data stored in an e-fuse array to other constituent elements of the semiconductor device that use the data of the e-fuse array in order to have the data stored in the e-fuse array, including diverse setup information and repair information.

6. 发明授权

US08644089B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08644089B2
公开(公告)日：2014-02-04
申请号：US13524524
申请日：2012-06-15
申请人： Taehyung Jung
发明人： Taehyung Jung
IPC分类号： G11C16/04
CPC分类号： G11C11/4087 , G11C11/406 , G11C11/4085
摘要： A semiconductor memory device selecting a half page based on a particular bit of a row address includes: an input unit for receiving the particular bit; a control signal generation unit for outputting a mode control signal in response to a signal related to a mode for selecting a whole page; first and second mode control units for transferring first and second output signals of the input unit corresponding to the particular bit and its inverse signal; a row precharge pulse generation unit for generating a row precharge pulse enabled in an initial period of a precharge duration; a first driving unit for pull-up/pull-down driving an output terminal corresponding to a first pre-decoding signal; a second driving unit for pull-up/pull-down driving an output terminal corresponding to a second pre-decoding signal; and first and second latch units for latching output signals of the first and second driving units.
摘要翻译：基于行地址的特定位选择半页的半导体存储器件包括：用于接收特定位的输入单元; 控制信号生成单元，用于响应于与用于选择整个页面的模式相关的信号输出模式控制信号; 第一和第二模式控制单元，用于传送与特定位对应的输入单元的第一和第二输出信号及其反相信号; 行预充电脉冲产生单元，用于产生在预充电持续时间的初始周期中使能的行预充电脉冲; 用于上拉/下拉驱动对应于第一预解码信号的输出端的第一驱动单元; 第二驱动单元，用于上拉/下拉驱动对应于第二预解码信号的输出端; 以及用于锁存第一和第二驱动单元的输出信号的第一和第二锁存单元。

7. 发明申请

US20130336073A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20130336073A1
公开(公告)日：2013-12-19
申请号：US13524524
申请日：2012-06-15
申请人： Taehyung JUNG
发明人： Taehyung JUNG
IPC分类号： G11C7/10
CPC分类号： G11C11/4087 , G11C11/406 , G11C11/4085
摘要： A semiconductor memory device selecting a half page based on a particular bit of a row address includes: an input unit for receiving the particular bit; a control signal generation unit for outputting a mode control signal in response to a signal related to a mode for selecting a whole page; first and second mode control units for transferring first and second output signals of the input unit corresponding to the particular bit and its inverse signal; a row precharge pulse generation unit for generating a row precharge pulse enabled in an initial period of a precharge duration; a first driving unit for pull-up/pull-down driving an output terminal corresponding to a first pre-decoding signal; a second driving unit for pull-up/pull-down driving an output terminal corresponding to a second pre-decoding signal; and first and second latch units for latching output signals of the first and second driving units.
摘要翻译：基于行地址的特定位选择半页的半导体存储器件包括：用于接收特定位的输入单元; 控制信号生成单元，用于响应于与用于选择整个页面的模式相关的信号输出模式控制信号; 第一和第二模式控制单元，用于传送与特定位对应的输入单元的第一和第二输出信号及其反相信号; 行预充电脉冲产生单元，用于产生在预充电持续时间的初始周期中使能的行预充电脉冲; 第一驱动单元，用于上拉/下拉驱动对应于第一预解码信号的输出端; 第二驱动单元，用于上拉/下拉驱动对应于第二预解码信号的输出端; 以及用于锁存第一和第二驱动单元的输出信号的第一和第二锁存单元。

8. 发明申请

US20130286754A1 Wordline Coupling Reduction Technique 有权
标题翻译：字线耦合减少技术
公开(公告)号：US20130286754A1
公开(公告)日：2013-10-31
申请号：US13457065
申请日：2012-04-26
申请人： TaeHyung Jung , BokMoon Kang
发明人： TaeHyung Jung , BokMoon Kang
IPC分类号： G11C8/08
CPC分类号： G11C8/08 , G11C5/063 , G11C7/12 , G11C16/24 , G11C16/26
摘要： A semiconductor memory includes a memory array having memory cells coupled to wordlines and bitlines. Each wordline has a left end and an opposing right end. A first wordline in every two adjacent wordlines has its left end connected to a left row driver and its right end connected to a right clamp circuit, and a second wordline in every two adjacent wordlines has its right end connected to a right row driver and its left end connected to a left clamp circuit, such that when the right clamp circuits are activated, the right clamp circuits clamp the corresponding wordline ends to a predetermined potential, and when the left clamp circuits are activated, the left clamp circuits clamp the corresponding wordline ends to the predetermined potential.
摘要翻译：半导体存储器包括具有耦合到字线和位线的存储器单元的存储器阵列。每个字线都有一个左端和一个相反的右端。每两个相邻字线中的第一个字线的左端连接到左行驱动器，其右端连接到右钳位电路，每两个相邻字线中的第二个字线的右端连接到右排驱动器，左端连接到左钳位电路，使得当右钳位电路被激活时，右钳位电路将相应的字线端钳位到预定电位，并且当左钳位电路被激活时，左钳位电路钳位相应的字线结束到预定的电位。

9. 发明授权

US08861294B2 Storage cell bridge screen technique 有权
标题翻译：存储单元桥接屏幕技术
公开(公告)号：US08861294B2
公开(公告)日：2014-10-14
申请号：US13540227
申请日：2012-07-02
申请人： TaeHyung Jung , KeeSoo Kim
发明人： TaeHyung Jung , KeeSoo Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C7/08 , G11C29/025
摘要： A semiconductor memory includes a circuit block that is configured to receive a test mode command, a first sense amplifier that is coupled to sense and amplify a state of a first memory cell when enabled, and a second sense amplifier that is coupled to sense and amplify a state of a second memory cell when enabled. In an active cycle, the circuit block generates one or more control signals in response to the test mode command that cause the second sense amplifier to be enabled a predetermined amount of time after the first sense amplifier is enabled.
摘要翻译：半导体存储器包括被配置为接收测试模式命令的电路块，耦合以在使能时耦合以感测和放大第一存储器单元的状态的第一读出放大器，以及耦合到感测和放大的第二读出放大器启用时第二存储器单元的状态。在有效周期中，电路块根据测试模式命令产生一个或多个控制信号，该命令使第二读出放大器在第一读出放大器被使能之后能够被预定的时间使能。

10. 发明申请

US20100202220A1 MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR PROVIDING BIT LINE EQUALIZATION VOLTAGES 有权
标题翻译：用于提供线路均衡电压的存储器电路，系统和方法
公开(公告)号：US20100202220A1
公开(公告)日：2010-08-12
申请号：US12692512
申请日：2010-01-22
申请人： Kuoyuan Peter HSU , TaeHyung Jung , Douk Hyoun Ryu , Young Suk Kim
发明人： Kuoyuan Peter HSU , TaeHyung Jung , Douk Hyoun Ryu , Young Suk Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C11/4076
摘要： A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a first bit line. At least one bit line equalization transistor is coupled between the first bit line and a second bit line. A bit line equalization circuit is coupled with the bit line equalization transistor. The bit line equalization circuit is configured for providing a pulse to the bit line equalization transistor to substantially equalize voltages of the first bit line and the second bit line during a standby period before an access cycle of the memory cell.
摘要翻译：存储电路包括至少一个用于存储表示数据的电荷的存储单元。存储单元与字线和第一位线耦合。至少一个位线均衡晶体管耦合在第一位线和第二位线之间。位线均衡电路与位线均衡晶体管耦合。位线均衡电路被配置为向位线均衡晶体管提供脉冲，以在存储单元的访问周期之前的待机期间基本上均衡第一位线和第二位线的电压。

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