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1. 发明申请

US20160086898A1 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US20160086898A1
公开(公告)日：2016-03-24
申请号：US14722742
申请日：2015-05-27
申请人： Jin-wook Jang , Se-jin Yoo , Sung-il Cho , Jae-ho Choi
发明人： Jin-wook Jang , Se-jin Yoo , Sung-il Cho , Jae-ho Choi
IPC分类号： H01L23/00 , H01L25/065 , H01L23/48 , H01L23/498 , H01L23/31
CPC分类号： H01L24/09 , H01L21/565 , H01L23/3128 , H01L23/3135 , H01L23/3142 , H01L23/315 , H01L23/481 , H01L23/49811 , H01L23/49838 , H01L23/49861 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L2224/0401 , H01L2224/05022 , H01L2224/05572 , H01L2224/131 , H01L2224/16146 , H01L2224/16227 , H01L2224/16237 , H01L2224/17181 , H01L2224/73204 , H01L2224/8192 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/141 , H01L2924/143 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/18161 , H01L2924/014
摘要： A semiconductor package includes a wiring substrate including a plurality of solder pads; a chip including a plurality of chip pads connected to the solder pads through a plurality of solders; a sealing layer configured to seal the chip and the solders, at least one void being between the solders; and a solder extrusion prevention layer on one sidewall of the solder exposed by the at least one void.
摘要翻译：半导体封装包括：包括多个焊盘的布线基板; 芯片，其包括通过多个焊料连接到焊盘的多个芯片焊盘; 密封层，其被构造成密封所述芯片和所述焊料，所述至少一个空隙在所述焊料之间; 以及在由所述至少一个空隙暴露的所述焊料的一个侧壁上的焊料挤出防止层。

2. 外观设计

USD741880S1 Display screen of a television receiver with graphical user interface 有权
标题翻译：具有图形用户界面的电视接收机的显示屏幕
公开(公告)号：USD741880S1
公开(公告)日：2015-10-27
申请号：US29428422
申请日：2012-07-31
申请人： Ji Young Hong , Gu Ang Jang , Jin Hae Choi , Kyung In Yang , Sung Il Cho
设计人： Ji Young Hong , Gu Ang Jang , Jin Hae Choi , Kyung In Yang , Sung Il Cho

3. 外观设计

USD735738S1 Television receiver display screen with graphical user interface 有权
标题翻译：电视接收机显示屏，带图形用户界面
公开(公告)号：USD735738S1
公开(公告)日：2015-08-04
申请号：US29428427
申请日：2012-07-31
申请人： Ji Young Hong , Gu Ang Jang , Jin Hae Choi , Kyung In Yang , Sung Il Cho
设计人： Ji Young Hong , Gu Ang Jang , Jin Hae Choi , Kyung In Yang , Sung Il Cho

4. 外观设计

USD721090S1 Display screen of a television receiver with graphic image 有权
标题翻译：具有图形图像的电视接收机的显示屏幕
公开(公告)号：USD721090S1
公开(公告)日：2015-01-13
申请号：US29428212
申请日：2012-07-27
申请人： Ji Young Hong , Gu Ang Jang , Jin Hae Choi , Kyung In Yang , Sung Il Cho
设计人： Ji Young Hong , Gu Ang Jang , Jin Hae Choi , Kyung In Yang , Sung Il Cho

5. 发明申请

US20140028567A1 DISPLAY DEVICE AND CONTROL METHOD THEREOF 有权
标题翻译：显示装置及其控制方法
公开(公告)号：US20140028567A1
公开(公告)日：2014-01-30
申请号：US14004642
申请日：2011-04-19
申请人： Sung Jong Park , Kyung Jin Kim , Sae Hun Jang , Gu-Ang Jang , Sung Il Cho , Yooseok Cho , Jiyoung Hong
发明人： Sung Jong Park , Kyung Jin Kim , Sae Hun Jang , Gu-Ang Jang , Sung Il Cho , Yooseok Cho , Jiyoung Hong
IPC分类号： G06F3/01
CPC分类号： G06F3/017 , G06F3/005 , G06F3/0236 , G06F3/0304
摘要： Disclosed are a display device and a control method thereof. The display device includes a display, a camera capturing a gesture in a three dimensional space; and a controller selectively displaying a virtual keyboard corresponding to a hand gesture for character input on the display when the captured gesture includes the hand gesture for the character input. Accordingly, the virtual keyboard corresponding to the hand gesture for the character input is displayed, so that the user may not perform an additional operation to display the virtual keyboard.
摘要翻译：公开了一种显示装置及其控制方法。显示装置包括显示器，在三维空间中拍摄手势的相机; 以及当捕获的手势包括用于字符输入的手势时，控制器选择性地显示对应于手势的虚拟键盘以便在显示器上输入字符。因此，显示对应于用于字符输入的手势的虚拟键盘，使得用户可能不执行附加操作来显示虚拟键盘。

6. 发明授权

US08461687B2 Semiconductor devices including bit line contact plug and buried channel array transistor, and semiconductor modules, electronic circuit boards and electronic systems including the same 有权
标题翻译：包括位线接触插头和掩埋沟道阵列晶体管的半导体器件，以及包括其的电子电路板和电子系统的半导体模块
公开(公告)号：US08461687B2
公开(公告)日：2013-06-11
申请号：US13072907
申请日：2011-03-28
申请人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
发明人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
IPC分类号： H01L29/40 , H01L29/66
CPC分类号： H01L23/528 , H01L23/535 , H01L27/1052 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L29/0649 , H01L29/42324 , H01L29/45 , H01L29/78 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
摘要翻译：具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管和周边晶体管上电极。位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。

7. 发明申请

US20110241102A1 SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND BURIED CHANNEL ARRAY TRANSISTOR, METHODS OF FABRICATING THE SAME, AND SEMICONDUCTOR MODULES, ELECTRONIC CIRCUIT BOARDS AND ELECTRONIC SYSTEMS INCLUDING THE SAME 有权
标题翻译：包括位线接触插头和布线通道阵列晶体管，其制造方法和半导体模块，电子电路板和包括其的电子系统的半导体器件
公开(公告)号：US20110241102A1
公开(公告)日：2011-10-06
申请号：US13072907
申请日：2011-03-28
申请人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
发明人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
IPC分类号： H01L29/78
CPC分类号： H01L23/528 , H01L23/535 , H01L27/1052 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L29/0649 , H01L29/42324 , H01L29/45 , H01L29/78 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
摘要翻译：具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管和周边晶体管上电极。位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。

8. 发明申请

US20110110174A1 System and Method of Operating a Memory Device 有权
标题翻译：操作存储器件的系统和方法
公开(公告)号：US20110110174A1
公开(公告)日：2011-05-12
申请号：US12617305
申请日：2009-11-12
申请人： Sung Il Cho , Sei Seung Yoon , Naveen Gundubogula , Mohamed H. Abu-Rahma , Dongkyu Park
发明人： Sung Il Cho , Sei Seung Yoon , Naveen Gundubogula , Mohamed H. Abu-Rahma , Dongkyu Park
IPC分类号： G11C7/00 , G11C8/08 , G11C7/02
CPC分类号： G11C11/419 , G11C7/08 , G11C7/14 , G11C7/22 , G11C7/222 , G11C7/227 , G11C8/08 , G11C11/418 , G11C2207/065
摘要： A system and method of operating a memory device is disclosed. In a particular embodiment, an apparatus is disclosed that includes a bit cell coupled to a first bit line and to a second bit line. The apparatus also includes a sense amplifier coupled to the first bit line and to the second bit line. The apparatus includes a loop circuit configured to provide a sense amplifier enable signal to the sense amplifier in response to receiving a first signal. The apparatus also includes a wordline enable circuit configured to provide a wordline enable signal to a wordline driver in response to receiving a second signal. The loop circuit receives the first signal before the wordline enable circuit receives the second signal.
摘要翻译：公开了一种操作存储器件的系统和方法。在特定实施例中，公开了一种包括耦合到第一位线和第二位线的位单元的装置。该装置还包括耦合到第一位线和第二位线的读出放大器。该装置包括一个环路电路，其被配置为响应于接收到第一信号向感测放大器提供读出放大器使能信号。该装置还包括字线使能电路，其被配置为响应于接收到第二信号而向字线驱动器提供字线使能信号。环路电路在字线使能电路接收到第二信号之前接收第一信号。

9. 发明授权

US07704828B2 Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07704828B2
公开(公告)日：2010-04-27
申请号：US11741639
申请日：2007-04-27
申请人： Jung-Min Oh , Jeong-Nam Han , Chang-Ki Hong , Kun-Tack Lee , Dae-Hyuk Kang , Sung-Il Cho
发明人： Jung-Min Oh , Jeong-Nam Han , Chang-Ki Hong , Kun-Tack Lee , Dae-Hyuk Kang , Sung-Il Cho
IPC分类号： H01L21/8242
CPC分类号： H01L28/91
摘要： A method of fabricating a semiconductor device is provided. The method includes forming a mold for forming a storage electrode, forming sacrificial spacers at side walls of openings in the mold, forming a conductive film for a storage electrode along the inside of the openings, removing the mold by a wet etching process, removing the sacrificial spacers by a dry etching process, and sequentially forming a dielectric film and an upper electrode on the storage electrode.
摘要翻译：提供一种制造半导体器件的方法。该方法包括形成用于形成存储电极的模具，在模具的开口的侧壁处形成牺牲隔离物，沿着开口的内部形成用于存储电极的导电膜，通过湿法蚀刻工艺移除模具，牺牲隔离物，并且在存储电极上依次形成电介质膜和上电极。

10. 发明授权

US07531449B2 Method of forming fine patterns using double patterning process 有权
标题翻译：使用双重图案化工艺形成精细图案的方法
公开(公告)号：US07531449B2
公开(公告)日：2009-05-12
申请号：US11730264
申请日：2007-03-30
申请人： Sang-joon Park , Yong-hyun Kwon , Jun Seo , Sung-il Cho , Chang-jin Kang , Jae-kyu Ha
发明人： Sang-joon Park , Yong-hyun Kwon , Jun Seo , Sung-il Cho , Chang-jin Kang , Jae-kyu Ha
IPC分类号： H01L21/4763
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L21/76897
摘要： A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, and a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns. The method then etches non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and then etches the selected portions of the material layer to form the plurality of contact holes.
摘要翻译：公开了一种在形成在基板上的材料层中形成多个接触孔的双重图案方法。该方法形成在材料层上沿第一方向以第一间距分开的平行多个第一硬掩模图案，与第一硬掩模图案交错并与第一硬掩模分离的自对准并行多个第二硬掩模图案通过缓冲层形成图案以形成复合掩模图案，以及与第一方向相交的第二方向的多个上掩模图案，以与复合掩模图案一起掩蔽缓冲层的选定部分。然后，该方法使用复合硬掩模图案和上掩模图案作为蚀刻掩模蚀刻缓冲层的未选择部分，以形成暴露材料层的选定部分的多个硬掩模孔，然后蚀刻所选择的部分所述材料层形成所述多个接触孔。

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