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1. 发明授权

US06990743B2 Process for monitoring measuring device performance 失效
公开(公告)号：US06990743B2
公开(公告)日：2006-01-31
申请号：US10230595
申请日：2002-08-29
申请人： Steve W. Bowes
发明人： Steve W. Bowes
IPC分类号： G01D18/00 , H01J37/26
CPC分类号： H01J37/28 , H01J2237/2814 , H01J2237/2826
摘要： The disclosed embodiments relate to calibrating a measuring device by comparing a set of master measurement data against a set of current measurement data. Adjustments are made to the measuring device based on the difference between the current measurement data and the master measurement data.

2. 发明授权

US06852456B2 Reducing asymmetrically deposited film induced registration error 失效
公开(公告)号：US06852456B2
公开(公告)日：2005-02-08
申请号：US10122555
申请日：2002-04-15
申请人： Erik Byers , Steve W. Bowes
发明人： Erik Byers , Steve W. Bowes
IPC分类号： G03F7/20 , G03F9/00 , G03C5/00
CPC分类号： G03F7/70633 , G03F7/70625 , G03F9/7003 , G03F9/7084
摘要： Methods, systems, products and apparatuses are disclosed herein relating to registration and asymmetrically deposited films, and more specifically, to reducing asymmetrically deposited film induced registration measurement error.

3. 发明授权

US06795747B2 Reducing asymmetrically deposited film induced registration error 失效
标题翻译：减少不对称沉积膜引起的配准误差
公开(公告)号：US06795747B2
公开(公告)日：2004-09-21
申请号：US10122786
申请日：2002-04-15
申请人： Erik Byers , Steve W. Bowes
发明人： Erik Byers , Steve W. Bowes
IPC分类号： G06F1900
CPC分类号： G03F7/70633 , G03F7/70625 , G03F9/7003 , G03F9/7084
摘要： Methods, systems, products and apparatuses are disclosed herein relating to registration and asymmetrically deposited films, and more specifically, to reducing asymmetrically deposited film induced registration measurement error.
摘要翻译：本文公开了关于配准和非对称沉积膜的方法，系统，产品和装置，更具体地，涉及减少不对称沉积的膜引发的注射测量误差。

4. 发明授权

US06465141B2 Method for improved lithographic critical dimension control 失效
标题翻译：改进光刻临界尺寸控制的方法
公开(公告)号：US06465141B2
公开(公告)日：2002-10-15
申请号：US10000040
申请日：2001-12-04
申请人： Ulrich C. Boettiger , Scott L. Light , Steve W. Bowes
发明人： Ulrich C. Boettiger , Scott L. Light , Steve W. Bowes
IPC分类号： G03F900
CPC分类号： G03F7/70483 , G02B26/02
摘要： A system and method for minimizing critical dimension errors on imaged wafers is described. After imaging and processing one or more wafers, the various critical dimensions are determined across the imaged exposure field and compared with the target critical dimensions to ascertain average critical dimension errors. The critical dimension error distribution across the field is modeled and the necessary exposure dose corrections are calculated to compensate the critical dimension errors. A pellicle is formed with light intensity modifying regions corresponding to the calculated local dose corrections. These regions alter the amount of light which is transmitted from a light source through a semiconductor mask onto the exposure fields of the wafers. As a consequence, the critical dimensions of the printed features are altered as well. The light intensity modifying region may be formed by depositing, such as by sputtering, particles which reflect or absorb light. Alternatively, the light intensity modifying region may be formed with an ink jet printer. Instead, a clear or grey-scaled pellicle may be used, and portions of it may be ablated to alter light transmission in certain areas.
摘要翻译：描述了用于最小化成像晶片上的临界尺寸误差的系统和方法。在成像和处理一个或多个晶片之后，在成像的曝光场上确定各种关键尺寸，并与目标临界尺寸进行比较以确定平均临界尺寸误差。对现场的关键尺寸误差分布进行建模，并计算必要的曝光剂量校正以补偿临界尺寸误差。形成具有对应于计算的局部剂量校正的光强度修饰区域的防护薄膜组件。这些区域将从光源通过半导体掩模传送到晶片的曝光场上的光量变化。因此，打印功能的关键尺寸也会改变。可以通过例如溅射沉积反射或吸收光的颗粒来形成光强度修饰区域。或者，可以用喷墨打印机形成光强度修改区域。相反，可以使用透明或灰度级的防护薄膜，并且其部分可能被消融以改变某些区域的光透射。

5. 发明授权

US06861367B2 Semiconductor processing method using photoresist and an antireflective coating 失效
标题翻译：使用光致抗蚀剂和抗反射涂层的半导体加工方法
公开(公告)号：US06861367B2
公开(公告)日：2005-03-01
申请号：US10719640
申请日：2003-11-21
申请人： Terry L. Gilton , Steve W. Bowes , John T. Moore , Joseph F. Brooks , Kristy A. Campbell
发明人： Terry L. Gilton , Steve W. Bowes , John T. Moore , Joseph F. Brooks , Kristy A. Campbell
IPC分类号： G03F7/09 , H01L21/027 , H01L21/308 , H01L21/768 , H01L21/4763
CPC分类号： G03F7/091 , H01L21/0276 , H01L21/3081 , H01L21/76802 , Y10S438/952
摘要： A semiconductor processing method includes forming an antireflective coating comprising Ge and Se over a substrate to be patterned. Photoresist is formed over the antireflective coating. The photoresist is exposed to actinic radiation effective to pattern the photoresist. The antireflective coating reduces reflection of actinic radiation during the exposing than would otherwise occur under identical conditions in the absence of the antireflective coating. After the exposing, the substrate is patterned through openings in the photoresist and the antireflective coating using the photoresist and the antireflective coating as a mask. In one implementation, after patterning the substrate, the photoresist and the antireflective coating are chemically etched substantially completely from the substrate using a single etching chemistry.
摘要翻译：半导体处理方法包括在待图案化的基板上形成包含Ge和Se的抗反射涂层。在抗反射涂层上形成光致抗蚀剂。光致抗蚀剂暴露于光化辐射，有效地对光致抗蚀剂进行图案化。抗反射涂层减少曝光期间光化辐射的反射，否则在不存在抗反射涂层的同一条件下会发生。曝光后，使用光致抗蚀剂和抗反射涂层作为掩模，将光刻胶和防反射涂层中的开口图案化基板。在一个实施方案中，在图案化基板之后，使用单一蚀刻化学法，使基板完全从基板上完全蚀刻光致抗蚀剂和抗反射涂层。

6. 发明授权

US06778275B2 Aberration mark and method for estimating overlay error and optical aberrations 有权
公开(公告)号：US06778275B2
公开(公告)日：2004-08-17
申请号：US10081966
申请日：2002-02-20
申请人： Steve W. Bowes
发明人： Steve W. Bowes
IPC分类号： G01B1100
CPC分类号： G01B11/26
摘要： An aberration mark for use in an optical photolithography system, and a method for estimating overlay errors and optical aberrations. The aberration mark includes an inner polygon pattern and an outer polygon pattern, wherein each of the inner and outer polygon patterns include a center, and two sets of lines and spaces having a different feature size and pitch that surround the outer polygon pattern. The aberration mark can be used to estimate overlay errors and optical aberrations. In some embodiments, the mark can also be used with scatterometry or scanning electron microscope devices. In other embodiments, the mark can be used to monitor aberrations of a lens in an optical photolithography system.

7. 发明授权

US06545829B1 Method and device for improved lithographic critical dimension control 有权
公开(公告)号：US06545829B1
公开(公告)日：2003-04-08
申请号：US09642019
申请日：2000-08-21
申请人： Ulrich C. Boettiger , Scott L. Light , Steve W. Bowes
发明人： Ulrich C. Boettiger , Scott L. Light , Steve W. Bowes
IPC分类号： G02B522
CPC分类号： G03F7/70483 , G02B26/02
摘要： A system and method for minimizing critical dimension errors on imaged wafers is described. After imaging and processing one or more wafers, the various critical dimensions are determined across the imaged exposure field and compared with the target critical dimensions to ascertain average critical dimension errors. The critical dimension error distribution across the field is modeled and the necessary exposure dose corrections are calculated to compensate the critical dimension errors. A pellicle is formed with light intensity modifying regions corresponding to the calculated local dose corrections. These regions alter the amount of light which is transmitted from a light source through a semiconductor mask onto the exposure fields of the wafers. As a consequence, the critical dimensions of the printed features are altered as well. The light intensity modifying region may be formed by depositing, such as by sputtering, particles which reflect or absorb light. Alternatively, the light intensity modifying region may be formed with an ink jet printer. Instead, a clear or grey-scaled pellicle may be used, and portions of it may be ablated to alter light transmission in certain areas.

8. 发明授权

US06538830B2 Method and device for improved lithographic critical dimension control 失效
公开(公告)号：US06538830B2
公开(公告)日：2003-03-25
申请号：US09998166
申请日：2001-12-03
申请人： Ulrich C. Boettiger , Scott L. Light , Steve W. Bowes
发明人： Ulrich C. Boettiger , Scott L. Light , Steve W. Bowes
IPC分类号： G02B522
CPC分类号： G03F7/70483 , G02B26/02
摘要： A system and method for minimizing critical dimension errors on imaged wafers is described. After imaging and processing one or more wafers, the various critical dimensions are determined across the imaged exposure field and compared with the target critical dimensions to ascertain average critical dimension errors. The critical dimension error distribution across the field is modeled and the necessary exposure dose corrections are calculated to compensate the critical dimension errors. A pellicle is formed with light intensity modifying regions corresponding to the calculated local dose corrections. These regions alter the amount of light which is transmitted from a light source through a semiconductor mask onto the exposure fields of the wafers. As a consequence, the critical dimensions of the printed features are altered as well. The light intensity modifying region may be formed by depositing, such as by sputtering, particles which reflect or absorb light. Alternatively, the light intensity modifying region may be formed with an ink jet printer. Instead, a clear or grey-scaled pellicle may be used, and portions of it may be ablated to alter light transmission in certain areas.

9. 发明授权

US07064080B2 Semiconductor processing method using photoresist and an antireflective coating 有权
公开(公告)号：US07064080B2
公开(公告)日：2006-06-20
申请号：US10071425
申请日：2002-02-08
申请人： Terry L. Gilton , Steve W. Bowes , John T. Moore , Joseph F. Brooks , Kristy A. Campbell
发明人： Terry L. Gilton , Steve W. Bowes , John T. Moore , Joseph F. Brooks , Kristy A. Campbell
IPC分类号： H01L21/302
CPC分类号： G03F7/091 , H01L21/0276 , H01L21/3081 , H01L21/76802 , Y10S438/952
摘要： A semiconductor processing method includes forming an antireflective coating comprising Ge and Se over a substrate to be patterned. Photoresist is formed over the antireflective coating. The photoresist is exposed to actinic radiation effective to pattern the photoresist. The antireflective coating reduces reflection of actinic radiation during the exposing than would otherwise occur under identical conditions in the absence of the antireflective coating. After the exposing, the substrate is patterned through openings in the photoresist and the antireflective coating using the photoresist and the antireflective coating as a mask. In one implementation, after patterning the substrate, the photoresist and the antireflective coating are chemically etched substantially completely from the substrate using a single etching chemistry.

10. 发明授权

US06730444B2 Needle comb reticle pattern for critical dimension and registration measurements using a registration tool and methods for using same 失效
标题翻译：使用注册工具进行关键尺寸和注册测量的针梳掩模版图案及其使用方法
公开(公告)号：US06730444B2
公开(公告)日：2004-05-04
申请号：US09874615
申请日：2001-06-05
申请人： Steve W. Bowes
发明人： Steve W. Bowes
IPC分类号： G03F900
CPC分类号： G03F7/70625 , G03F1/44 , G03F7/70633 , H01L2223/54453
摘要： Needle comb reticle patterns for use in both critical dimension analysis and registration analysis with a registration tool are disclosed. One embodiment of a needle comb reticle pattern includes a box-in-box feature flanked on two adjacent sides by needle combs with tapered flat-tipped needles. Another embodiment of a needle comb reticle pattern includes a box-in-box feature flanked on two adjacent sides by needle combs with tapered flat-tipped needles and flanked on the other two adjacent sides by reference bars. Yet another embodiment of a needle comb reticle pattern includes two complementary needle comb reticle subpatterns, each subpattern including a box-in-box feature with four flanking needle combs. A registration tool can be used with the needle combs and reference bars to measure critical dimension of a semiconductor process. The registration tool can also be used with the box-in-box feature to measure registration between two adjacent layers during semiconductor fabrication. Reticles, fields within reticles, masks and wafers including the needle comb reticle pattern of the present invention are also disclosed. Additionally, methods for analyzing critical dimension and registration and characterizing needle comb reticle measurements to critical dimension using the needle comb reticle patterns of the present invention are also disclosed.
摘要翻译：公开了用于使用注册工具进行临界尺寸分析和配准分析的针梳状掩模版图案。针梳光罩图案的一个实施例包括通过具有锥形平头针的针梳而在两个相邻侧面上的箱内盒特征。针梳子掩模图案的另一实施例包括通过具有锥形平头针的针梳并且在另外两个相邻侧通过参考杆两侧相邻的两个相邻侧上的箱内盒特征。针刺掩模版图案的另一个实施例包括两个互补的针梳光栅子图案，每个子图案包括具有四个侧面针梳的盒子盒特征。针梳和参考杆可以使用配准工具来测量半导体工艺的临界尺寸。配准工具也可以与盒装箱功能一起使用，以测量半导体制造期间两个相邻层之间的配准。还公开了网状物，掩模版内的场，掩模和包括本发明的针梳掩模版图案的晶片。此外，还公开了使用本发明的针梳光罩图案分析临界尺寸和配准并将针梳标线测量值表征到关键尺寸的方法。

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