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1. 发明授权

US08345236B2 Method and apparatus for determining the particles contained in a particle stream 有权
标题翻译：用于确定颗粒物流中所含颗粒的方法和装置
公开(公告)号：US08345236B2
公开(公告)日：2013-01-01
申请号：US12299744
申请日：2007-04-30
申请人： Stefan Dietrich , Guenter Eckardt , Michael Koehler
发明人： Stefan Dietrich , Guenter Eckardt , Michael Koehler
IPC分类号： G01N15/02
CPC分类号： G06M1/101 , G01N15/1429 , G01N15/1459 , G01N2015/1075 , G01N2015/1402
摘要： A method and an apparatus for determining the particle content of a particle stream using a source of light and two receivers arranged offset from one another in the flow direction of the particle stream. The receivers provide an electrical signal to an evaluation unit as a function of the radiation intensity which they receive, and this signal makes possible a determination of the flow velocity and particle size. Coincident passage of two particles is indicated by a pulse occurring in the signal due to a “roof collapse” in the pulse caused by a weakening of the radiation intensity as the particles pass a receiver.
摘要翻译：一种用于使用光源确定颗粒物流的颗粒含量的方法和装置，以及在颗粒物流的流动方向彼此偏移地设置的两个接收器。接收器根据接收到的辐射强度向评估单元提供电信号，并且该信号使流动速度和粒度的确定成为可能。两个颗粒的重合通道由信号中出现的脉冲表示，这是由于当颗粒通过接收器时由辐射强度的弱化引起的脉冲中的屋顶塌陷。

2. 发明授权

US08036059B2 Semiconductor memory circuit, circuit arrangement and method for reading out data 有权
标题翻译：半导体存储器电路，电路布置和读出数据的方法
公开(公告)号：US08036059B2
公开(公告)日：2011-10-11
申请号：US11594562
申请日：2006-11-08
申请人： Stefan Dietrich
发明人： Stefan Dietrich
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1036 , G11C7/106 , G11C7/1066
摘要： A circuit arrangement for reading out data time delayed from a semiconductor memory comprises a common data input at which read data, which are read out of a semiconductor memory, are present and a data buffer FIFO for buffering the read data. The buffer FIFI comprises a plurality of FIFO modules each comprising a plurality of individual FIFO cells. Each FIFO module can be addressed via respective allocated first input and output pointers and each FIFO cell can be addressed via respective allocated second input and output pointers. The circuit arrangement further comprises a controllable read latency generator generating the first and second output pointers for driving the FIFO modules and FIFO cells with a read latency predetermined with reference to the first and second input pointers, respectively, and a common data output at which the read data are present time-delayed in dependence on the predetermined read latency.
摘要翻译：用于读出从半导体存储器延迟的数据的电路装置包括：公共数据输入端，存储从半导体存储器读出的读取数据，以及用于缓冲读取数据的数据缓冲器FIFO。缓冲器FIFI包括多个FIFO模块，每个FIFO模块包括多个单独的FIFO单元。可以通过相应分配的第一输入和输出指针来寻址每个FIFO模块，并且可以通过相应分配的第二输入和输出指针来寻址每个FIFO单元。该电路装置还包括一个可控读延迟发生器，分别产生用于驱动FIFO模块和FIFO单元的第一和第二输出指针，其具有参考第一和第二输入指针预定的读等待时间，以及公共数据输出，读取数据根据预定的读取等待时间延迟。

3. 发明申请

US20080306723A1 Emulated Combination Memory Device 审中-公开
标题翻译：仿真组合存储器件
公开(公告)号：US20080306723A1
公开(公告)日：2008-12-11
申请号：US12126738
申请日：2008-05-23
申请人： Luca De Ambroggi , Stefan Dietrich , Peter Schroegmeier , Marco Redaelli
发明人： Luca De Ambroggi , Stefan Dietrich , Peter Schroegmeier , Marco Redaelli
IPC分类号： G06F9/455 , G06F12/02 , G06F12/00
CPC分类号： G11C11/005 , G11C13/0004 , G11C13/0033 , G11C14/0045 , G11C14/0063
摘要： An integrated circuit memory device and a method of providing access to multiple memory types within a single integrated circuit memory device are described. In various embodiments, the integrated circuit memory device includes a non-volatile memory array having a first emulated memory region and a second emulated memory region, and a controller having an interface. The memory device is configured to emulate a first emulated memory type and a second emulated memory type. The memory device is further configured to store data in the first emulated memory region when the memory device emulates the first emulated memory type, and in the second emulated memory region when the memory device emulates the second emulated memory type.
摘要翻译：描述了在单个集成电路存储器件内提供对多种存储器类型的访问的集成电路存储器件和方法。在各种实施例中，集成电路存储器件包括具有第一仿真存储器区域和第二仿真存储器区域的非易失性存储器阵列，以及具有接口的控制器。存储器设备被配置为模拟第一仿真存储器类型和第二仿真存储器类型。存储器设备还被配置为当存储器设备模拟第一仿真存储器类型时，以及当存储器件模拟第二仿真存储器类型时，在第二仿真存储器区域中，将数据存储在第一仿真存储器区域中。

4. 发明授权

US07454559B2 Filtering bit position in a memory 失效
标题翻译：在存储器中过滤位位置
公开(公告)号：US07454559B2
公开(公告)日：2008-11-18
申请号：US11386377
申请日：2006-03-22
申请人： Stefan Dietrich
发明人： Stefan Dietrich
IPC分类号： G06F12/00
CPC分类号： G11C7/1078 , G06F5/10 , G11C7/04 , G11C7/1021 , G11C7/1051 , G11C7/1069 , G11C7/1096 , G11C11/406 , G11C11/40615 , G11C19/287 , G11C2207/005
摘要： A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter, a write training block and a temporary data register. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for moving the FIFO output pointer based on data read from the FIFO cells. The temporary data register is for storing a single bit representing one or more bits in each FIFO cell.
摘要翻译：存储器包括多个先进先出（FIFO）单元，输出指针计数器，写入训练块和临时数据寄存器。输出指针计数器用于切换FIFO单元格中FIFO输出指针的值。写入训练块用于根据从FIFO单元读取的数据移动FIFO输出指针。临时数据寄存器用于存储表示每个FIFO单元中的一个或多个位的单个位。

5. 发明申请

US20070247929A1 MEMORY DEVICE AND METHOD OF OPERATING SUCH 失效
标题翻译：存储器件及其操作方法
公开(公告)号：US20070247929A1
公开(公告)日：2007-10-25
申请号：US11735928
申请日：2007-04-16
申请人： Paul Wallner , Stefan Dietrich , Peter Gregorius
发明人： Paul Wallner , Stefan Dietrich , Peter Gregorius
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1057 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A memory device comprising a memory cell array; an input circuit for receiving command data and providing drive signals to the memory cell array; an output buffer for buffering data read out from the memory cell array; and a timer for driving the output buffer such that the buffered data are provided at an output after a predetermined time interval has elapsed, the predetermined time interval beginning with the provision of the drive signals.
摘要翻译：一种存储器件，包括存储单元阵列; 用于接收命令数据并向存储单元阵列提供驱动信号的输入电路; 用于缓冲从存储单元阵列读出的数据的输出缓冲器; 以及用于驱动输出缓冲器的定时器，使得在经过预定时间间隔之后的输出处提供缓冲数据，从提供驱动信号开始的预定时间间隔。

6. 发明申请

US20070166501A1 Structured paper release liner, adhesive-backed article assembly and method of making same 有权
标题翻译：结构纸剥离衬垫，粘合剂背衬制品组装及其制造方法
公开(公告)号：US20070166501A1
公开(公告)日：2007-07-19
申请号：US10595835
申请日：2004-11-19
申请人： David Seitz , Kanta Kumar , Larry Meixner , Mieczyslaw Mazurek , Stefan Dietrich
发明人： David Seitz , Kanta Kumar , Larry Meixner , Mieczyslaw Mazurek , Stefan Dietrich
IPC分类号： B32B37/00 , B32B37/26 , B32B33/00 , G11B5/64 , B32B7/12
CPC分类号： D21H27/001 , B32B7/10 , B32B27/10 , C09J7/38 , C09J7/403 , C09J2201/28 , C09J2201/606 , C09J2400/283 , D21H19/32 , D21H19/40 , D21H19/826 , D21H27/02 , Y10T428/14 , Y10T428/1476 , Y10T428/24 , Y10T428/24355 , Y10T428/24364 , Y10T428/24446 , Y10T428/24455 , Y10T428/24479 , Y10T428/24521 , Y10T428/24554 , Y10T428/24628 , Y10T428/28 , Y10T428/2839
摘要： A structured paper release liner (10) for use with an article (44) backed with a pressure sensitive adhesive, an adhesive-backed article assembly (42) and methods of making each are disclosed. The liner (10) comprises a piece of paper (14) having a release side free of a structural support layer, a back side, and a structured release surface (48) having a pattern formed into the paper (14) on the release side. A release material is on the structured release surface of the paper. The pattern formed in the paper (14) is designed so as to form fluid egress channels in a bonding surface of the pressure sensitive adhesive (46). The fluid egress channels define a structured bonding surface (48) having exit pathways for fluid to bleed out from behind the article when the structured bonding surface (48) is adhered to or otherwise disposed on a substrate.
摘要翻译：公开了一种与用压敏粘合剂背衬的物品（44）一起使用的结构化纸张释放衬垫（10），粘合剂背衬制品组件（42）和制造每个的方法。衬垫（10）包括具有释放侧的一张纸（14），其没有结构支撑层，背面和结构化释放表面（48），其具有形成在释放侧上的纸张（14）中的图案。释放材料在纸的结构化释放表面上。在纸（14）中形成的图案被设计成在压敏粘合剂（46）的粘合表面中形成流体流出通道。流体出口通道限定了结构化结合表面（48），其具有出口通道，用于当结构化结合表面（48）粘附或以其他方式设置在基底上时，流体从制品后部渗出。

7. 发明申请

US20070121393A1 Semiconductor memory circuit, circuit arrangement and method for reading out data 有权
标题翻译：半导体存储器电路，电路布置和读出数据的方法
公开(公告)号：US20070121393A1
公开(公告)日：2007-05-31
申请号：US11594562
申请日：2006-11-08
申请人： Stefan Dietrich
发明人： Stefan Dietrich
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1036 , G11C7/106 , G11C7/1066
摘要： A circuit arrangement for reading out data time delayed from a semiconductor memory comprises a common data input at which read data, which are read out of a semiconductor memory, are present and a data buffer FIFO for buffering the read data. The buffer FIFI comprises a plurality of FIFO modules each comprising a plurality of individual FIFO cells. Each FIFO module can be addressed via respective allocated first input and output pointers and each FIFO cell can be addressed via respective allocated second input and output pointers. The circuit arrangement further comprises a controllable read latency generator generating the first and second output pointers for driving the FIFO modules and FIFO cells with a read latency predetermined with reference to the first and second input pointers, respectively, and a common data output at which the read data are present time-delayed in dependence on the predetermined read latency.
摘要翻译：用于读出从半导体存储器延迟的数据的电路装置包括：公共数据输入端，存储从半导体存储器读出的读取数据，以及用于缓冲读取数据的数据缓冲器FIFO。缓冲器FIFI包括多个FIFO模块，每个FIFO模块包括多个单独的FIFO单元。可以通过相应分配的第一输入和输出指针来寻址每个FIFO模块，并且可以通过相应分配的第二输入和输出指针来寻址每个FIFO单元。该电路装置还包括一个可控读延迟发生器，分别产生用于驱动FIFO模块和FIFO单元的第一和第二输出指针，其具有参考第一和第二输入指针预定的读等待时间，以及公共数据输出，读取数据根据预定的读取等待时间延迟。

8. 发明申请

US20070104014A1 Circuit arrangement for generating an n-bit output pointer, semiconductor memory and method for adjusting a read latency 失效
标题翻译：用于产生n位输出指针的电路装置，半导体存储器和用于调整读延迟的方法
公开(公告)号：US20070104014A1
公开(公告)日：2007-05-10
申请号：US11593234
申请日：2006-11-06
申请人： Stefan Dietrich
发明人： Stefan Dietrich
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G06F5/10 , G11C7/222
摘要： A circuit arrangement for generating an n-bit output pointer in a semiconductor memory comprises at least one m-bit interface for accepting an m-bit reference signal, at least one m-bit binary counter, a decoder arrangement connected downstream of the binary counter, and outputs for providing the bits of the output pointer. The reference signal comprises an information regarding a read latency to be adjusted utilizing the output pointer, the at least one counter provides an m-bit counter reading signal comprising a current counter reading, and the decoder arrangement comprises a plurality of decoder devices each comparing the current counter reading signal with a reference value which is associated with a respective of the decoder devices. Each decoder device provides one bit of the output pointer on the basis of the comparing.
摘要翻译：用于在半导体存储器中产生n位输出指针的电路装置包括至少一个用于接受m位参考信号的m位接口，至少一个m位二进制计数器，连接在二进制计数器下游的解码器装置，以及用于提供输出指针的位的输出。所述参考信号包括关于使用所述输出指针进行调整的读等待时间的信息，所述至少一个计数器提供包括当前计数器读数的m位计数器读取信号，并且所述解码器装置包括多个解码器装置，具有与各个解码器装置相关联的参考值的当前计数器读取信号。每个解码器装置在比较的基础上提供一位输出指针。

9. 发明授权

US07140774B2 Slidable fastener bearing assembly 有权
标题翻译：可滑动紧固件轴承组件
公开(公告)号：US07140774B2
公开(公告)日：2006-11-28
申请号：US10788597
申请日：2004-02-27
申请人： Robert K. Galkiewicz , Stefan Dietrich
发明人： Robert K. Galkiewicz , Stefan Dietrich
IPC分类号： F16C29/02
CPC分类号： A44B18/0053 , F16B5/07
摘要： A bearing assembly is disclosed, which comprises at least two slidable fasteners interengaged with at least two bearing pieces such that the slidable fasteners have substantially unrestricted biaxial motion relative to one another. The bearing pieces are comprised of self-closable fastener film comprising a base sheet and a multiplicity of ribs projecting from the base sheet, wherein the flat side of the first bearing piece is attached to the flat side of the second bearing piece such that the ribs of the first bearing piece are not parallel relative to the ribs of the second bearing piece.
摘要翻译：公开了一种轴承组件，其包括与至少两个轴承件相互接合的至少两个可滑动紧固件，使得可滑动紧固件相对于彼此具有基本上无限制的双轴运动。轴承片由可自动关闭的紧固件薄片组成，包括基片和从基片突出的多个肋，其中第一轴承片的平坦侧附接到第二轴承片的平坦侧，使得肋第一轴承片的第一轴承片的肋不相对于第二轴承片的肋平行。

10. 发明授权

US07120818B2 Method and device for data transfer 有权
公开(公告)号：US07120818B2
公开(公告)日：2006-10-10
申请号：US10103517
申请日：2002-03-22
申请人： Stefan Dietrich , Peter Schrögmeier , Sabine Kieser , Christian Weis
发明人： Stefan Dietrich , Peter Schrögmeier , Sabine Kieser , Christian Weis
IPC分类号： G06F1/04
CPC分类号： G11C7/1078 , G06F13/4068 , G11C7/1051 , G11C7/1057 , G11C7/1084
摘要： Data transfer is effected on an internal and/or on an external transfer path with or in a semiconductor component, such as a semiconductor memory. A first multiplexer/demultiplexer codes a data sequence by defining a current level and a voltage level for a data signal. The coded sequence is then transferred on the transfer path synchronously with a clock signal and is decoded in a second multiplexer/demultiplexer by evaluation of the received current level and of the received voltage level. From this, the transferred data sequence is determined.

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