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1. 发明申请

US20070232041A1 Integrated circuit device gate structures having charge storing nano crystals in a metal oxide dielectric layer and methods of forming the same 审中-公开
标题翻译：在金属氧化物介电层中具有电荷存储纳米晶体的集成电路器件栅极结构及其形成方法
公开(公告)号：US20070232041A1
公开(公告)日：2007-10-04
申请号：US11510058
申请日：2006-08-25
申请人： Sam-jong Choi , Kyoo-chul Cho , Soo-yeol Choi , Yong-kwon Kim , Young-soo Park , Chan-kook In , Hae-jin Park , Sang-Sig Kim
发明人： Sam-jong Choi , Kyoo-chul Cho , Soo-yeol Choi , Yong-kwon Kim , Young-soo Park , Chan-kook In , Hae-jin Park , Sang-Sig Kim
IPC分类号： H01L21/3205
CPC分类号： H01L21/265 , B82Y10/00 , G11C2216/06 , H01L21/28167 , H01L21/28185 , H01L21/28194 , H01L29/1037 , H01L29/40114 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/66825 , H01L29/7881 , H01L29/7885 , H01L29/7887
摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a metal oxide dielectric layer on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the dielectric layer to form a charge storing region in the dielectric layer with a tunnel dielectric layer under the charge storing region and a capping dielectric layer above the charge storing region. The substrate including the metal oxide dielectric layer is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region. A gate electrode layer is formed on the dielectric layer.
摘要翻译：形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成金属氧化物介电层。将元素周期表第4组的选定元素的离子注入到电介质层中，并且具有小于约0.5厘米每秒（cm 2 / s）的热扩散率，形成电荷存储区在具有电荷存储区域下方的隧道介电层的电介质层和电荷存储区域上方的封盖电介质层。包含金属氧化物介电层的基板被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体。在电介质层上形成栅极电极层。

2. 发明申请

US20050259246A1 Apparatus for inspecting a surface and methods thereof 审中-公开
标题翻译：用于检查表面的装置及其方法
公开(公告)号：US20050259246A1
公开(公告)日：2005-11-24
申请号：US11133367
申请日：2005-05-20
申请人： Tae-Soo Kang , Kyoo-Chul Cho , Soo-Yeol Choi , Sam-Dong Choi
发明人： Tae-Soo Kang , Kyoo-Chul Cho , Soo-Yeol Choi , Sam-Dong Choi
IPC分类号： H01L21/66 , G01N21/47 , G01N21/88 , G01N21/95
CPC分类号： G01N21/47 , G01N21/9501
摘要： An apparatus and method for detecting a surface status. The method includes generating first and second pulse sequences and irradiating the first and second pulse sequences into a given surface. Light from the first and second pulses may be scattered by the given surface and analyzed to determine the status of the given surface. The apparatus includes a device for generating pulses which contact a given surface at different incident angles. The light scattered from the pulses may be analyzed at a determining part to determine a status of the given surface. In another embodiment, the method includes generating first and second pulse sequences and adjusting a path of at least a portion of at least one of the first and second pulse sequences such that the first and second pulse sequences are incident upon a given surface at different incident angles.
摘要翻译：一种用于检测表面状态的装置和方法。该方法包括产生第一和第二脉冲序列并将第一和第二脉冲序列照射到给定的表面中。来自第一和第二脉冲的光可以被给定的表面散射并且被分析以确定给定表面的状态。该装置包括用于产生以不同入射角接触给定表面的脉冲的装置。可以在确定部分分析从脉冲散射的光以确定给定表面的状态。在另一个实施例中，该方法包括产生第一和第二脉冲序列并且调整第一和第二脉冲序列中的至少一个的至少一部分的路径，使得第一和第二脉冲序列在不同事件处入射到给定表面上角度。

3. 发明申请

US20050016470A1 Susceptor and deposition apparatus including the same 审中-公开
标题翻译：受体和包括其的沉积装置
公开(公告)号：US20050016470A1
公开(公告)日：2005-01-27
申请号：US10898306
申请日：2004-07-26
申请人： Tae-Soo Kang , Soo-Yeol Choi , Kyoo-Chul Cho , Gi-Jung Kim , Jin-Ho Kim , Tae-Yeol Heo
发明人： Tae-Soo Kang , Soo-Yeol Choi , Kyoo-Chul Cho , Gi-Jung Kim , Jin-Ho Kim , Tae-Yeol Heo
IPC分类号： H01L21/205 , C23C16/00 , C23C16/458 , C30B25/12 , C30B31/14
CPC分类号： C23C16/4584 , C30B25/12 , C30B31/14
摘要： A susceptor for use in a deposition apparatus includes a recess in which a wafer is received, and a stress-reducing bumper disposed along the side of the recess. The stress-reducing bumper is of material having ductility at a relatively high temperature. Therefore, when the wafer contacts the stress-reducing bumper, such as may occur due to thermal expansion of the wafer during processing, the force of the impact on the wafer is minimized by an elastic deformation of the stress-reducing bumper. As a result, defects, such as slip dislocations at the outer peripheral edge of the wafer, are prevented.
摘要翻译：用于沉积设备的感受体包括其中容纳晶片的凹部和沿着凹部的侧面设置的减小应力的保险杠。减压保险杠是在较高温度下具有延性的材料。因此，当晶片接触减压保险杠时，例如由于晶片在加工过程中的热膨胀而可能发生的，通过减小应力的保险杠的弹性变形使得对晶片的冲击力最小化。结果，防止了晶片外周边缘处的滑移位错等缺陷。

4. 发明申请

US20070246775A1 SOI SUBSTRATE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译： SOI衬底及其形成方法
公开(公告)号：US20070246775A1
公开(公告)日：2007-10-25
申请号：US11739351
申请日：2007-04-24
申请人： Young-Soo PARK , Kyoo-Chul CHO , Soo-Yeol CHOI , Tae-Soo KANG , Yoon-Hee LEE
发明人： Young-Soo PARK , Kyoo-Chul CHO , Soo-Yeol CHOI , Tae-Soo KANG , Yoon-Hee LEE
IPC分类号： H01L27/12
CPC分类号： H01L29/66795 , H01L29/66772 , H01L29/7841 , H01L29/785 , H01L29/7851 , H01L29/78639 , H01L29/7881
摘要： Provided are an SOI substrate, memory devices using the SOI substrate, and a method of manufacturing the same. The SOI substrate includes a thermal oxide layer pattern which minimizes leakage current but allows back biasing and heat dissipation through the substrate. The SOI substrate also includes a metal-gettering site to further minimize leakage current.
摘要翻译：提供了SOI衬底，使用SOI衬底的存储器件及其制造方法。 SOI衬底包括热氧化层图案，其使漏电流最小化，但允许通过衬底的背偏置和散热。 SOI衬底还包括金属吸杂位点以进一步最小化泄漏电流。

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