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1. 发明申请

US20120239887A1 METHOD AND APPARATUS FOR MEMORY CONTROL 审中-公开
标题翻译：用于记忆控制的方法和装置
公开(公告)号：US20120239887A1
公开(公告)日：2012-09-20
申请号：US13049670
申请日：2011-03-16
申请人： James R. MAGRO , Shwetal A. PATEL
发明人： James R. MAGRO , Shwetal A. PATEL
IPC分类号： G06F12/00
CPC分类号： G06F13/1673
摘要： A method is provided for issuing subcommands to a memory module using unassigned bits in a memory control protocol. A buffer component within the memory module receives the subcommands and modifies a state of the memory module accordingly. This allows, for example, selectively powering down individual ranks of the memory module (e.g., an LRDIMM memory module). Unassigned bits in a JEDEC-compliant ZQ calibration command set may be used for implementing such subcommands.
摘要翻译：提供了一种用于使用存储器控制协议中的未分配位向存储器模块发出子命令的方法。存储器模块内的缓冲器组件接收子命令并相应地修改存储器模块的状态。这允许例如选择性地断电存储器模块（例如，LRDIMM存储器模块）的各个等级。符合JEDEC标准的ZQ校准命令集中的未分配位可用于实现这些子命令。

2. 发明授权

US08019921B2 Intelligent memory buffer 有权
标题翻译：智能内存缓冲区
公开(公告)号：US08019921B2
公开(公告)日：2011-09-13
申请号：US12271213
申请日：2008-11-14
申请人： Shwetal A. Patel
发明人： Shwetal A. Patel
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/14
摘要： A technique reduces cost, complexity and/or power consumption of a memory system by including intelligence in a memory buffer circuit of the memory system. An apparatus includes a memory buffer circuit configured to selectively operate in one of a plurality of modes. In a first mode, the memory buffer circuit is configured to interface to a first type of memory device, is configured to enable an input circuit of the memory buffer circuit, and is configured to drive on a terminal of a memory interface of the memory buffer circuit a version of a signal received by the input circuit during a memory operation. In a second mode, the memory buffer circuit is configured to interface to the first type of memory device, is configured to disable the input circuit, and is configured to drive a signal on the terminal during the memory operation.
摘要翻译：一种技术通过在存储器系统的存储器缓冲电路中包括智能来降低存储器系统的成本，复杂性和/或功率消耗。一种装置包括被配置为选择性地以多种模式之一操作的存储器缓冲器电路。在第一模式中，存储器缓冲器电路被配置为与第一类型的存储器件接口，被配置为使能存储器缓冲器电路的输入电路，并且被配置为在存储器缓冲器的存储器接口的终端上驱动在存储器操作期间电路由输入电路接收的信号的版本。在第二模式中，存储器缓冲电路被配置为与第一类型的存储器件接口，被配置为禁用输入电路，并且被配置为在存储器操作期间驱动终端上的信号。

3. 发明申请

US20100125681A1 INTELLIGENT MEMORY BUFFER 有权
标题翻译：智能内存缓冲区
公开(公告)号：US20100125681A1
公开(公告)日：2010-05-20
申请号：US12271213
申请日：2008-11-14
申请人： Shwetal A. Patel
发明人： Shwetal A. Patel
IPC分类号： G06F3/00
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/14
摘要： A technique reduces cost, complexity and/or power consumption of a memory system by including intelligence in a memory buffer circuit of the memory system. An apparatus includes a memory buffer circuit configured to selectively operate in one of a plurality of modes. In a first mode, the memory buffer circuit is configured to interface to a first type of memory device, is configured to enable an input circuit of the memory buffer circuit, and is configured to drive on a terminal of a memory interface of the memory buffer circuit a version of a signal received by the input circuit during a memory operation. In a second mode, the memory buffer circuit is configured to interface to the first type of memory device, is configured to disable the input circuit, and is configured to drive a signal on the terminal during the memory operation.
摘要翻译：一种技术通过在存储器系统的存储器缓冲器电路中包括智能来降低存储器系统的成本，复杂性和/或功率消耗。一种装置包括被配置为选择性地以多种模式之一操作的存储器缓冲器电路。在第一模式中，存储器缓冲器电路被配置为与第一类型的存储器件接口，被配置为使能存储器缓冲器电路的输入电路，并且被配置为在存储器缓冲器的存储器接口的终端上驱动在存储器操作期间电路由输入电路接收的信号的版本。在第二模式中，存储器缓冲电路被配置为与第一类型的存储器件接口，被配置为禁用输入电路，并且被配置为在存储器操作期间驱动终端上的信号。

4. 发明授权

US08260992B2 Reducing simultaneous switching outputs using data bus inversion signaling 有权
标题翻译：使用数据总线反转信号降低同时开关输出
公开(公告)号：US08260992B2
公开(公告)日：2012-09-04
申请号：US12758301
申请日：2010-04-12
申请人： Glenn A. Dearth , Shwetal A. Patel
发明人： Glenn A. Dearth , Shwetal A. Patel
IPC分类号： G06F13/36 , G06F13/362 , G06F13/372 , G06F1/26 , G06F1/32 , H03M5/00
CPC分类号： G06F13/4234 , Y02D10/14 , Y02D10/151
摘要： An apparatus includes a plurality of data lines defining a data bus for communicating data. A controller is operable to communicate a plurality of data transfers over the data bus using a plurality of data time slots, wherein for at least a subset of the data time slots the controller is operable to communicate an associated data bus inversion indicator indicating that bits communicated during the associated data time slot are inverted, the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and the controller is operable to communicate a global data bus inversion indicator indicating an inversion of the data bus inversion vector.
摘要翻译：一种装置包括定义用于传送数据的数据总线的多条数据线。控制器可操作以使用多个数据时隙通过数据总线传送多个数据传输，其中对于数据时隙的至少一个子集，控制器可操作地传送指示相关位的相关联的数据总线反相指示符在相关联的数据时隙反转期间，用于数据传输子集的数据总线反相指示器被分组为数据总线反向向量，并且控制器可操作地传送指示数据总线的反转的全局数据总线反向指示符反演矢量。

5. 发明申请

US20110252171A1 REDUCING SIMULTANEOUS SWITCHING OUTPUTS USING DATA BUS INVERSION SIGNALING 有权
标题翻译：使用数据总线反相信号减少同时切换输出
公开(公告)号：US20110252171A1
公开(公告)日：2011-10-13
申请号：US12758301
申请日：2010-04-12
申请人： Glenn A. Dearth , Shwetal A. Patel
发明人： Glenn A. Dearth , Shwetal A. Patel
IPC分类号： G06F13/372
CPC分类号： G06F13/4234 , Y02D10/14 , Y02D10/151
摘要： An apparatus includes a plurality of data lines defining a data bus for communicating data. A controller is operable to communicate a plurality of data transfers over the data bus using a plurality of data time slots, wherein for at least a subset of the data time slots the controller is operable to communicate an associated data bus inversion indicator indicating that bits communicated during the associated data time slot are inverted, the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and the controller is operable to communicate a global data bus inversion indicator indicating an inversion of the data bus inversion vector.
摘要翻译：一种装置包括定义用于传送数据的数据总线的多条数据线。控制器可操作以使用多个数据时隙通过数据总线传送多个数据传输，其中对于数据时隙的至少一个子集，控制器可操作地传送指示相关位的相关联的数据总线反相指示符在相关联的数据时隙反转期间，用于数据传输子集的数据总线反相指示器被分组为数据总线反向向量，并且控制器可操作地传送指示数据总线的反转的全局数据总线反向指示符反演矢量。

6. 发明申请

US20090091963A1 MEMORY DEVICE 审中-公开
标题翻译：内存设备
公开(公告)号：US20090091963A1
公开(公告)日：2009-04-09
申请号：US11867208
申请日：2007-10-04
申请人： Shwetal A. Patel
发明人： Shwetal A. Patel
IPC分类号： G11C5/06
CPC分类号： G11C7/1048 , G06F13/4243 , G11C5/04 , G11C5/063 , H04L25/0298 , Y02D10/14 , Y02D10/151
摘要： A first DRAM device comprises a first input connected to a first trace line to receive an address signal and a second input is connected to receive an operating voltage, such as Vdd. A second DRAM device comprises a first input connected to the first trace line to receive the address signal and a second input to receive the operating voltage. A first signal termination structure is connected to the first trace line, wherein the first signal termination structure is to terminate the first trace line to the operating voltage.
摘要翻译：第一DRAM器件包括连接到第一迹线以接收地址信号的第一输入端，第二输入端连接以接收诸如Vdd的工作电压。第二DRAM器件包括连接到第一迹线以接收地址信号的第一输入端和用于接收工作电压的第二输入端。第一信号终端结构连接到第一迹线，其中第一信号终端结构是将第一迹线终止于工作电压。

7. 发明授权

US07421525B2 System including a host connected to a plurality of memory modules via a serial memory interconnect 有权
标题翻译：系统包括通过串行存储器互连连接到多个存储器模块的主机
公开(公告)号：US07421525B2
公开(公告)日：2008-09-02
申请号：US10842296
申请日：2004-05-10
申请人： R. Stephen Polzin , Frederick D. Weber , Gerald R. Talbot , Larry D. Hewitt , Richard W. Reeves , Shwetal A. Patel , Ross V. La Fetra , Dale E. Gulick , Mark D. Hummel , Paul C. Miranda
发明人： R. Stephen Polzin , Frederick D. Weber , Gerald R. Talbot , Larry D. Hewitt , Richard W. Reeves , Shwetal A. Patel , Ross V. La Fetra , Dale E. Gulick , Mark D. Hummel , Paul C. Miranda
IPC分类号： G06F13/00 , G06F13/28 , G06F12/00 , G11C5/06
CPC分类号： G06F13/4243 , G06F12/0215 , G06F12/0862 , G06F13/1626 , G06F2212/6022
摘要： A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.
摘要翻译：一种系统，包括耦合到串行连接的存储器模块链的主机。在一个实施例中，每个存储器模块包括用于控制对存储器模块上的多个存储器芯片的访问的存储器控制集线器。存储器模块通过多个存储器链路串联地连接到主机。每个存储器链路可以包括用于向主机传送事务的上行链路和用于将在主机处发起的事务传送到链路中的下一个存储器模块的下行链路。上行链路和下行链路可以使用包括控制和配置分组和存储器访问分组的分组来传送事务。存储器控制集线器可以在第二存储器链路的第二下行链路上传送在第一存储器链路的第一下行链路上接收的事务，而与解码事务无关。

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